A transistor biasing circuit including a first controller configured to receive a sensor signal generated based on the performance of one or more transistors of a digital circuit and to compare the sensor signal with a reference signal and to generate a first biasing voltage control signal; a first actuator configured to generate a first biasing voltage based on the first biasing voltage control signal; a second actuator configured to generate a second biasing voltage based on a second biasing voltage control signal; and a second controller configured to generate the second biasing voltage control signal based on an intermediate voltage level generated based on the first and second biasing voltages.

A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

A body bias voltage generating circuit includes a current mirror circuit configured to generate and input a target current to a target semiconductor element, the target semiconductor element configured to be set to a turned-on state; and a charge pump circuit including an oscillator configured to output a clock signal based on a result of comparing an output voltage of the target semiconductor element with a reference voltage, and at least one charge pump outputting a body bias voltage to each of a plurality of semiconductor elements, wherein each of the plurality of semiconductor elements is the same as or is the same type as the target semiconductor element.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry connected between a high voltage source and a low voltage source. The core circuitry may include multiple transistors including a first transistor of a first polarity type and a second transistor of a second polarity type that is different than the first polarity type. The integrated circuit may include voltage regulation circuitry connected between an external positive voltage source and ground. The voltage regulation circuitry may operate to provide the low voltage source to the core circuitry. The low voltage source may be equal to or higher than ground. The voltage regulation circuitry may further operate to body bias the multiple transistors with a single voltage that is applied to a body terminal of the first transistor and the second transistor.

A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

The present disclosure provides a pump system of a DRAM and a method for operating the same. The pump system includes a pump device and a spare pump assembly. The pump device provides a current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate. The spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate.

The present disclosure provides a pump system of a DRAM and a method for operating the same. The pump system includes a pump device and a spare pump assembly. The pump device provides a current sufficient to allow a bank of the DRAM to operate at a normal refresh rate without other spare pump devices in response to a normal instruction which indicates that the bank is instructed to operate at the normal refresh rate. The spare pump assembly includes a first spare pump device configured to provide, in combination with the pump device, a current sufficient to allow the bank to operate at a first refresh rate greater than the normal refresh rate in response to a first instruction which indicates that the bank is instructed to operate at the first refresh rate.

A semiconductor device includes a substrate, a circuit having a transistor formed on the substrate, an oscillation circuit generating a frequency signal, a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit, and a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit.