Disclosed is an electrostatic protection circuit, an array substrate and a display device. The electrostatic protection circuit includes a first electrostatic discharge end, a second electrostatic discharge end and a signal line connecting end; a first discharge sub-circuit coupled between the first electrostatic discharge end and the signal line connecting end; and a second discharge sub-circuit coupled between the second electrostatic discharge end and the signal line connecting end. Each of the first discharge sub-circuit and the second discharge sub-circuit comprises at least one MOSFET, and gates of all MOSFETs comprised in the first discharge sub-circuit and the second discharge sub-circuit are not coupled with any one of the first electrostatic discharge end, the second electrostatic discharge end and the signal line connecting end.

An electrostatic discharge protection device includes a first well region, a second well region, a first doped region, and a first heavily doped region. The first well region and the second well region are disposed in a semiconductor substrate. The first doped region is disposed in the first well region and the second well region. The first heavily doped region is disposed in the first doped region in the first well region. The first well region and the first doped region have a first conductivity type, and the second well region and the first heavily doped region have a second conductivity type that is the opposite of the first conductivity type.

An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.

An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.

In some aspects, the techniques described herein relate to an electromagnetic interference (EMI) filter circuit including: an input terminal; an output terminal; an electrical ground terminal; a resistor electrically coupled between the input terminal and the output terminal; a first bipolar transistor including: a collector terminal electrically coupled with the input terminal; an emitter terminal electrically coupled with the electrical ground terminal; and a base terminal that is electrically floating; and a second bipolar transistor including: a collector terminal electrically coupled with the output terminal; an emitter terminal electrically coupled with the electrical ground terminal; and a base terminal that is electrically floating.

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

The present disclosure relates to the technical field of integrated circuits, and provides a test structure of an integrated circuit, to solve the technical problem of difficulty in measuring electrical parameters of the integrated circuit. The test structure of an integrated circuit includes: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region. There is a first distance between the first P-type heavily doped region and the second P-type heavily doped region, and there is a second distance between the second P-type heavily doped region and the N-type heavily doped region. Electrical parameters of the integrated circuit are obtained by adjusting at least one of the first distance and the second distance.

A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.