An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A system having a device for conducting an electrostatic discharge (ESD) current from a designated pin node. The system includes first and second pin nodes, and a switching device having a first switching threshold. The switching device includes a first, terminal coupled to a reference node, and a second terminal, coupled to the first pin node to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the reference node exceeding the first switching threshold. The switching device further includes a third terminal, coupled to the second pin node, to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the second pin node exceeding a second switching threshold.

A protection device may include a semiconductor substrate and a thyristor-type device, formed within the semiconductor substrate, where the thyristor device extends from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate. The protection device may include a first PN diode, formed within the semiconductor substrate; and a second PN diode, formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode.

An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

A POR circuit includes a voltage divider coupleable between a supply voltage and a POR trace, including a first element coupled between the supply voltage and a node, and a second element coupled between the node and the POR trace. A switch is drain to source coupled between the POR trace and a reference voltage. A first decoupling capacitor is coupled between the POR trace and the reference voltage. A second decoupling capacitor is coupled between the node and the reference voltage. ESD protection for an integrated circuit includes charging a node of a voltage divider coupled between a supply voltage and a POR trace to a predetermined percentage of the supply voltage, decoupling high frequency noise with a first decoupling capacitor between the POR trace and a reference voltage, and decoupling low frequency noise with a second decoupling capacitor between the node and the reference voltage.

Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first doped region in the first epitaxial layer and forming a second doped region surrounding the first doped region in the first epitaxial layer, wherein the semiconductor substrate and the first doped region are both of a first doping type, the buried layer and the first epitaxial layer are both of a second doping type, the first doping type is opposite to the second doping type, the first doped region and the second doped region are formed using a same first mask. The method uses the same mask to form an emitter region of the open-base bipolar transistor, and to form a barrier doped region at the periphery of the emitter region, so that the manufacture cost is reduced and the parasitic capacitance of the ESD protection device is decreased.