A terminal protection circuit of a semiconductor chip, including a first pad serving as a ground terminal of the semiconductor chip, a ground line extending along an outer periphery of the semiconductor chip and being connected to the first pad, and an overcurrent sensing circuit. The overcurrent sensing circuit has a second pad, a threshold voltage generating circuit, a comparator having inverting and non-inverting input terminals respectively connected to the threshold voltage generating circuit and the second pad, the comparator comparing a current detection signal and a threshold voltage received respectively at the non-inverting and inverting input terminals, a first input protection element connected between the second pad and a first position on the chip-peripheral ground line, and a potential shift element connected between the inverting input terminal of the comparator and the first position, for shifting the threshold voltage thereat according to a potential at the first position.

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

According to an aspect, there is provided an apparatus comprising: a bulk-controlled switch circuit comprising a first transistor coupled to a load and having a source coupled to a source voltage and a drain coupled to a drain voltage, a second transistor and a third transistor coupled, in parallel with the first transistor, to one another in series between the source voltage and the drain voltage, wherein a bulk of the first transistor is coupled with bulks of the second transistor and the third transistor, wherein a gate of the second transistor is coupled to the source voltage via a first impedance circuit and a gate of the third transistor is coupled to the drain voltage via a second impedance circuit to form a comparator switch controlled by the source voltage and the drain voltage and to dynamically switch a greater one of the source voltage and the drain voltage to the load; a first current generator circuit and a second current generator circuit; a first current mirror circuit biased by the first current generator circuit, responsive to the source voltage, and configured to trigger the second transistor to couple the source voltage to the load when the source voltage is above the drain voltage; a second current mirror circuit biased by the second current generator circuit, responsive to the drain voltage, and configured to trigger the third transistor to couple the drain voltage to the load when the drain voltage is above the source voltage.

An ESD protection circuit includes a power MOS transistor disposed between a first line and a second line, a clamp circuit disposed between the first line and a first node to which a gate of the power MOS transistor is coupled, a first resistor disposed between the first node and the second line, a MOS transistor disposed between the first node and the second line, a third line supplied with a third potential generated by a constant-voltage circuit of the protection target circuit, and a second resistor and a first capacitor coupled in series between a second node coupled to the third line and the second line, wherein when defining a junction between the second resistor and the first capacitor as a third node, a gate of the MOS transistor is coupled to the third node.

A circuit includes a switch coupled between a configuration terminal and an internal node. In a method of operation, the configuration terminal of the circuit is coupled to an internal node during a configuration phase and decoupled from the internal node during normal operation.

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.