An integrated circuit apparatus includes a pad via which an AC signal is inputted or outputted, a circuit that overlaps with the pad in the plan view, protective wiring provided between the pad and the circuit, and a resistor having one end electrically coupled to the protective wiring and another end electrically coupled to an electric charge discharging path.

An electrostatic discharge protection device is provided. In particular, the present disclosure relates to a semiconductor device that is particularly useful for ESD protection purposes. The semiconductor device further includes a second electronic component integrated on the semiconductor body and being spaced apart from the first electronic component, the second electronic component includes a first secondary region of the first charge type and a second secondary region of the second charge type arranged adjacent to the first secondary region, and the second secondary region is electrically connected to the second device terminal; and a first capacitive element, a first terminal thereof being electrically connected to the second primary region, and a second terminal thereof being electrically connected to the first secondary region.

An array substrate of a display device includes a pixel electrode layer on a substrate, which includes active pixel electrodes in an active display region; outermost active pixel electrodes include a first active pixel electrode including a first pixel electrode edge and a second pixel electrode edge; in a first direction, the first pixel electrode edge is between the second pixel electrode edge and a frame region. One of the array substrate and an opposite substrate of the display device includes a common electrode layer including a first extended common electrode which includes a first extended portion extending beyond the first active pixel electrode; a first extended portion edge of the first extended portion and a first substrate edge of the substrate respectively extend in a second direction; in the first direction, the first extended portion edge is located between the first substrate edge and the first pixel electrode edge.

The present disclosure provides a light-emitting substrate, a backlight and a display device. The light-emitting substrate includes a light-emitting region and a peripheral region surrounding the light-emitting region. The peripheral region includes a first area, the first area is located between a first side of the light-emitting substrate and the light-emitting region, the light-emitting substrate further includes a first signal line, the first signal line includes at least one selected from a group consisting of a first portion and a second portion, the first portion of the first signal line extends along a first direction in the first area, the second portion of the first signal line extends into the light-emitting region, the first portion and the second portion of the first signal line are connected when the first signal line includes the first portion and the second portion.

The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.

An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.