In general, according to one embodiment, a protection circuit includes first and second power lines, first and second controllers, a first transistor, and a detector. The first controller includes a first resistor element, a capacitor, first, second, and third inverters. The second controller includes third transistor. One end of the third transistor is coupled to the second power line. The other end of the third transistor is coupled to each of the output end of the first inverter and the input end of the second inverter.

The present disclosure relates to a semiconductor device, including a first source/drain region, a second source/drain region, a base region, a first electrostatic discharge region and a second electrostatic discharge region. The first source/drain region and the second source/drain region are configured to receive a first power voltage and a second power voltage, and are formed on the base region. The first electrostatic discharge region includes a first doped region and a first well. The first doped region is configured to receive the second power voltage, and formed in the first well. The second electrostatic discharge region includes a second doped region and a second well. The second doped region is configured to receive the first power voltage, and formed in the second well. The first source/drain region and the second source/drain region are disposed between the first electrostatic discharge region and the second electrostatic discharge region.

A semiconductor device includes a semiconductor layer, a first region of a first conductivity type formed in the semiconductor layer and connected to a ground potential, a second region of a second conductivity type formed in the semiconductor layer, an insulating film formed on the semiconductor layer and covering the first region and the second region, an internal circuit, signal terminal for driving the internal circuit or to be driven by the internal circuit, a first wiring connecting the internal circuit and the signal terminal, a resistance element formed on the insulating film and interposed halfway through the first wiring, the resistance element including a first resistor facing the second region across the insulating film, and a second wiring connected to the first wiring on a side closer to the signal terminal than the resistance element and connecting the first wiring and the second region.

A MOSFET is provided, including a semiconductor body having a first major surface, a trench extending into the body from the first major surface to a gate region, the body including: a source region of a first conductivity type adjacent a sidewall of the trench at the first major surface, a drain region of the first conductivity type adjacent the trench distant from the source region, and a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent the sidewall of the trench between the source region and the drain region. The semiconductor body includes an Electro Static Discharge (ESD) region of the first conductivity type spaced apart from the trench and extending from the first major surface towards, but not into, the drain region. The ESD region includes a first region of the second conductivity type connected to the gate region.

The present application discloses an electro-static discharge protection structure, which includes an N-well and a P-well formed in a substrate. Upper parts and middle parts of the N-well and the P-well are isolated by shallow trench isolation (STI), and lower parts adjoin. The upper part of the N-well to form an N-well P-type heavily doped region adjacent to the STI. The upper part of the N-well to form an N-well N-type heavily doped region far away from the STI. The upper part of the P-well forms a P-well P-type heavily doped region adjacent to the STI. The N-well P-type heavily doped region and the N-well N-type heavily doped region are short-circuited to form an anode of the electro-static discharge protection structure. The P-well P-type heavily doped region is used as a cathode of the electro-static discharge protection structure. The present application can realize no snapback effect.

The present disclosure generally relates to the combination of MEMS intrinsic technology with specifically designed solid state ESD protection circuits in state of the art solid state technology for RF applications. Using ESD protection in MEMS devices has some level of complexity in the integration which can be seen by some as a disadvantage. However, the net benefits in the level of overall performance for insertion loss, isolation and linearity outweighs the disadvantages.

According to one embodiment, an integrated circuit includes a first power supply line, a protection circuit, an internal circuit, a second transistor, and a shutoff control circuit. A first power supply voltage is supplied to the first power supply line. The protection circuit is connected to the first power supply line. The internal circuit includes a first transistor whose breakdown voltage is lower than the first power supply voltage. A drain or a source of the first transistor is connected to the first power supply line. The second transistor is on the first power supply line between the protection circuit and the internal circuit and is configured to switch between conduction and non-conduction states to connect and disconnect the protection circuit and the internal circuit from one another along the first power supply line. The shutoff control circuit is configured to turn off the second transistor during an ESD operation.

A display device includes a substrate that includes a display area and a peripheral area outside the display area, a display element on the display area, a peripheral circuit on the peripheral area, the peripheral circuit including a thin film transistor, a first shielding layer on the peripheral circuit. and a second shielding layer on the first shielding layer. At least one of the first shielding layer and the second shielding layer includes a hole. One shielding layer of the first shielding layer and the second shielding layer includes the hole and overlaps the other one of the first shielding layer and the second shielding layer.

A switch chip includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is electrically coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire.

A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.