A display device may include a substrate, a pixel, a transistor, a data line, a connection line, a pad, and an electrostatic discharge protection circuit. The substrate may include a display area and a pad area. The pad area may overlap the display area. The pixel may be supported by the display area and may include a pixel electrode. The data line may be electrically connected through the transistor to the pixel electrode. The connection line may be supported by the display area and may be electrically connected through the data line to the transistor. The pad may be supported by the pad area and may be electrically connected through the connection line to the data line. The display area and the pad area may be positioned between the connection line and the pad. The electrostatic discharge protection circuit may be electrically connected to the connection line.

The present technology relates to a semiconductor device and a manufacturing method therefor, a solid-state imaging element and electronic equipment that make it possible to suppress breakdown of a side wall insulating film by charge damage to suppress short-circuiting. The semiconductor device according to an aspect of the present technology includes a first semiconductor substrate on which a given circuit is formed, a second semiconductor substrate, and through electrodes that electrically connect the first semiconductor substrate and the second semiconductor substrate to each other. The through electrode is formed such that a through-hole is opened through a protection diode structure formed in the first semiconductor substrate, an insulating film is deposited on a side wall of the through-hole, and an electrode material is then filled inside the through-hole in which the insulating film is deposited. The present technology can be applied, for example, to a CMOS image sensor.

A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming a plurality of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing a first etch step; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth metal layer above; forming a connection to the second metal layer which includes a via through the second level; forming a fifth metal layer above, where some second transistors include a metal gate, and the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.

A MOSFET is provided, including a semiconductor body having a first major surface, a trench extending into the body from the first major surface to a gate region, the body including: a source region of a first conductivity type adjacent a sidewall of the trench at the first major surface, a drain region of the first conductivity type adjacent the trench distant from the source region, and a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent the sidewall of the trench between the source region and the drain region. The semiconductor body includes an Electro Static Discharge (ESD) region of the first conductivity type spaced apart from the trench and extending from the first major surface towards, but not into, the drain region. The ESD region includes a first region of the second conductivity type connected to the gate region.

The present application discloses an electro-static discharge protection structure, which includes an N-well and a P-well formed in a substrate. Upper parts and middle parts of the N-well and the P-well are isolated by shallow trench isolation (STI), and lower parts adjoin. The upper part of the N-well to form an N-well P-type heavily doped region adjacent to the STI. The upper part of the N-well to form an N-well N-type heavily doped region far away from the STI. The upper part of the P-well forms a P-well P-type heavily doped region adjacent to the STI. The N-well P-type heavily doped region and the N-well N-type heavily doped region are short-circuited to form an anode of the electro-static discharge protection structure. The P-well P-type heavily doped region is used as a cathode of the electro-static discharge protection structure. The present application can realize no snapback effect.

The present disclosure generally relates to the combination of MEMS intrinsic technology with specifically designed solid state ESD protection circuits in state of the art solid state technology for RF applications. Using ESD protection in MEMS devices has some level of complexity in the integration which can be seen by some as a disadvantage. However, the net benefits in the level of overall performance for insertion loss, isolation and linearity outweighs the disadvantages.

An electrostatic discharge (ESD) device may include a semiconductor substrate including a first region, a second region, and a device isolation structure. The first region may include a first impurity region having a first conductivity type, a second impurity region having a second conductivity type opposite the first conductivity type, a first base well, and a first well in the first base well. The device isolation structure may be between the first and second impurity regions. The first base well may surround the first impurity region, the second impurity region, and lower portions of the device isolation structure in the substrate. The first well may have the first conductivity type. The first well may be spaced apart from the device isolation structure in a first direction with a portion of the first base well therebetween.

A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.