A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Certain aspects of the present disclosure generally relate to techniques for adjusting or setting a capacitance-versus-voltage (C-V) characteristic of a variable capacitor. For example, certain aspects of the present disclosure provide a capacitor device. The capacitor device generally includes a first variable capacitor and a second variable capacitor, each comprising a first terminal and a second terminal. In certain aspects, the second terminal of the second variable capacitor is coupled to the first terminal of the first variable capacitor, and the first terminal of the first variable capacitor is coupled to at least one biasing voltage node. In some cases, a decoupling capacitor may be coupled to the first terminal of the first variable capacitor.

Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a semiconductor region, an insulative layer disposed above the semiconductor region, and a first non-insulative region disposed above the insulative layer. In certain aspects, a second non-insulative region is disposed adjacent to the semiconductor region, and a control region is disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region. In certain aspects, the first non-insulative region is disposed above a first portion of the semiconductor region and a second portion of the semiconductor region, and the first portion and the second portion of the semiconductor region are disposed adjacent to a first side and a second side, respectively, of the control region or the second non-insulative region.

An accumulation-mode MOS varactor is formed with a standard CMOS process and having an anti-symmetric-CV curve. The asymmetric varactor (ASVAR) can efficiently generate even-order harmonics while simultaneously suppressing odd-order harmonics over broad bandwidths. This is achieved without degradation of dynamic cut-off frequency. The improved cut-off frequency of the asymmetric varactor results in efficient even-harmonic generation well into sub-millimeter or terahertz frequencies. This and the inherent adaptive-CV features of the asymmetric varactor result in even-harmonic generation with process variation resilience and can also be utilized for frequency response shaping and for optimizing performance at various driving conditions.

Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.

A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.

Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.