Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

An integrated circuit (e.g., a stacked capacitor) achieves higher capacitor density without additional area consumption. The integrated circuit includes a metal-oxide-semiconductor capacitor (MOSCAP), a metal-oxide-metal capacitor (MOMCAP) and a metal-insulator-metal capacitor (MIMCAP) stacked together. The MOSCAP includes a gate and source/drain (S/D) regions. The MOMCAP is included in back-end-of-line (BEOL) layers over the MOSCAP or supported by the MOSCAP.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having isolation structures therein and a capacitor structure located on a top surface of the isolation structure. The capacitor structure comprises a semiconductor material pattern and an insulator pattern inlaid in the semiconductor material pattern. The semiconductor material pattern and the insulator pattern are located at a same horizontal level on the isolation structure.

A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.

Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.

A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.