A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications.

A heterojunction bipolar transistor includes: a substrate; a base mesa disposed on the substrate, wherein the base mesa includes a collector layer and a base layer disposed on the collector layer, and wherein in a top view, the base layer includes a first edge and a second edge opposite to the first edge; an emitter layer disposed on the base layer; a base electrode disposed on the substrate and connected to the base layer; a dielectric layer disposed on the base electrode, wherein a first via hole is formed in the dielectric layer at the first edge of the base layer, and a second via hole is formed in the dielectric layer at the second edge of the base layer; and a conductive feature disposed on the dielectric layer, wherein the conductive feature is connected to the base electrode through the first via hole and the second via hole.

A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.

A low noise amplifier, LNA, including a silicon on insulator, SOI, substrate having a buried oxide, BOX, layer, wherein the SOI substrate includes a bulk region within which the buried oxide layer is removed. The SOI substrate is a high resistance, HR, SOI substrate including a silicon handle wafer having a resistivity greater than 3 k?-cm. The low noise amplifier, LNA, further has a bipolar transistor located in the bulk region, and a thick metal layer for connecting to the LNA.

An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.

A microfluidic device can include a base an outer surface of which forms one or more enclosures for containing a fluidic medium. The base can include an array of individually controllable transistor structures each of which can comprise both a lateral transistor and a vertical transistor. The transistor structures can be light activated, and the lateral and vertical transistors can thus be photo transistors. Each transistor structure can be activated to create a temporary electrical connection from a region of the outer surface of the base (and thus fluidic medium in the enclosure) to a common electrical conductor. The temporary electrical connection can induce a localized electrokinetic force generally at the region, which can be sufficiently strong to move a nearby micro-object in the enclosure.

A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane; a first conductivity type first semiconductor region; a first conductivity type second semiconductor region between the first semiconductor region and the first plane; a second conductivity type third semiconductor region and a fourth semiconductor region between the second semiconductor region and the first plane; a first conductivity type fifth semiconductor region between the third semiconductor region and the first plane; a first conductivity type sixth semiconductor region type between the fourth semiconductor region and the first plane; a first conductivity type seventh semiconductor region between the third semiconductor region and the fourth semiconductor region, between the first semiconductor region and the first plane, and having impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region; first and a second gate electrode; first and second gate insulating film.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which differs from the first BEOL stack, is determined such that, when the second BEOL stack is coupled with the emitter of the bipolar junction transistor, the first current ratio is changed to a second current ratio. The change from the first current ratio to the second current ratio, which is based on the change from the first layout for the first BEOL stack to the second layout for the second BEOL stack, is accomplished without changing a front-end-of-line (FEOL) layout of the bipolar junction transistor.

A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.