A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of Al.sub.xGa.sub.1-xAs, Al.sub.xGa.sub.1-xAs.sub.1-yN.sub.y, Al.sub.xGa.sub.1-xAs.sub.1-zP.sub.z, Al.sub.xGa.sub.1-xAs.sub.1-wSb.sub.w, and In.sub.rAl.sub.xGa.sub.1-x-rAs, x having a highest value between 0.05≤x≤0.4, and y, z, r, w≤0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.

A microfluidic device can include a base an outer surface of which forms one or more enclosures for containing a fluidic medium. The base can include an array of individually controllable transistor structures each of which can comprise both a lateral transistor and a vertical transistor. The transistor structures can be light activated, and the lateral and vertical transistors can thus be photo transistors. Each transistor structure can be activated to create a temporary electrical connection from a region of the outer surface of the base (and thus fluidic medium in the enclosure) to a common electrical conductor. The temporary electrical connection can induce a localized electrokinetic force generally at the region, which can be sufficiently strong to move a nearby micro-object in the enclosure.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.

A power semiconductor switch includes a cross-trench structure associated with at least one IGBT cell. The cross-trench structure merge at least one control trench, at least one dummy trench and at least one further trench of at least one IGBT cell to each other. The cross-trench structure overlaps at least partially along a vertical direction with trenches of the at least one IGBT-cell.

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.