A 3D semiconductor device a first level, where the first level includes a first layer which includes first transistors, where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one first ElectroStatic Discharge (ESD) circuit, and where the first level includes at least one second ESD circuit.

A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.

A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.

A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).

A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. A fourth semiconductor region adjoins the first semiconductor layers, is spaced apart from the first semiconductor region, and is arranged in the first device region between the first end of the first semiconductor region and the third semiconductor region.