A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.

The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established.

Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip. Moreover, the charging and discharging (writing/erasing), as well as the reading voltages are lower than those needed for CMOS based flash memory cells, due to the small nano-Schottky contact (301) and the small size of the nanoparticle for charge storage.

The present disclosure provides a method for manufacturing a fully self-aligned high-density 3D multi-layer memory, which relates to the technical field of memory manufacturing. The method includes the following steps: 1) forming a base structure; 2) grooving the base structure; 3) filling an insulating medium in the division groove; 4) deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, where the insulating medium is present between adjacent memory cell holes, and conductive medium layers and insulating medium layers of the base structure are exposed in the memory cell holes; and 5) disposing various layers of medium required by a preset memory structure layer by layer onto the inner walls of the memory cell holes. The semiconductor memory manufactured according to the present disclosure has high storage density.

Fabrication method of three-dimensional programmable memory in this invention is related to the memory fabrication technology. The present invention includes the following steps: 1) forming a basic structure; 2) forming an interdigital structure on the basic structure; 3) forming the cylindrical memory unit: according to the preset memory structure, the required intermediate medium layer materials are set layer by layer onto the inner wall of the cylindrical trench hole, and finally the core medium material is filled in the cylindrical trench hole to form the core medium material layer. The beneficial effects of the present invention are that the prepared semiconductor memory has high memory density, low process cost, being easy to fabricate.

The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.

A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established.