In a compact three-dimensional memory (3D-M.sub.C), a memory array and an above-substrate decoding stage thereof are formed on a same memory level. For the memory devices in the memory array, the overlap portion and the non-overlap portions of the x-line are both highly-conductive; for the decoding device in the above-substrate decoding stage, while the non-overlap portions are still highly-conductive, the overlap portion is semi-conductive.

The above-substrate decoding stage of a compact three-dimensional memory (3D-M.sub.c) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.

A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the microwave, millimeter wave or terahertz bands, that can be configured within a parallel plate structure, which solid state plasma monolithic microwave integrated circuit comprises: (i) a semiconductor dielectric substrate (3); (ii) parallel plates (1, 2) which comprise an upper conducting parallel plate (1) and a lower conducting parallel plate (2) and which parallel plates (1, 2) are used to guide an electromagnetic wave; (iii) an isolating trench which is between the parallel plates (1, 2), and which is used to contain a solid state plasma; (iv) a distinct p-doped region and a distinct n-doped region which are within a first semiconductor region defined by the isolating trench below the upper conducting parallel plate (1), and which are connected to two electrical bias terminals, where at least one electrical bias terminal forms a radio frequency short to the upper parallel plate (1); and a p or n doped region within a second semiconductor region defined by the isolating trench above the lower conducting parallel plate (2) and connected to a third electrical bias terminal, where the third electrical bias terminal forms a radio frequency short to the lower conducting parallel plate (2), and wherein; a solid state plasma is able to be controlled by voltage biasing of the three electrical bias terminals to either reflect, absorb or transmit an electromagnetic wave.

Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-M.sub.C) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

A device including a plurality of interconnected concentric coplanar diodes.

A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.