A solid-state image sensor including: a first impurity region of a first conductivity type; a plurality of second impurity regions of a second conductivity type disposed in the first impurity region and arranged in a first direction; and a light shielding layer that overlaps the first impurity region and does not overlap the second impurity regions in a plan view, wherein the first impurity region has a first portion between adjacent ones of the second impurity regions, the light shielding layer has a second portion that overlaps the first portion in a plan view, and a length of the second portion in the first direction is smaller than a length of the first portion in the first direction.

A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

A solid state image sensor includes a pixel array, as well as charge-to-voltage converters, reset gates, and amplifiers each shared by a plurality of pixels in the array. The voltage level of the reset gate power supply is set higher than the voltage level of the amplifier power supply. Additionally, charge overflowing from photodetectors in the pixels may be discarded into the charge-to-voltage converters. The image sensor may also include a row scanner configured such that, while scanning a row in the pixel array to read out signals therefrom, the row scanner resets the charge in the photodetectors of the pixels sharing a charge-to-voltage converter with pixels on the readout row. The charge reset is conducted simultaneously with or prior to reading out the signals from the pixels on the readout row.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

A photoelectric conversion device includes a waveguide member disposed above a photoelectric conversion unit, and an insulating member disposed above a substrate, and surrounding at least part of the waveguide member. The waveguide member has a first side face, a second side face, and a third side face, arranged in that order from the substrate. An angle of inclination of the first side face is smaller than an angle of inclination of the second side face. An angle of inclination of the third side face is smaller than the angle of inclination of the second side face. The angle of inclination of the second side face is smaller than 90 degrees.

Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.

There is provided an imaging element includes a photoelectric conversion unit that includes a first electrode, a photoelectric conversion layer, and a second electrode, in which the photoelectric conversion unit further includes a charge storage electrode that has an opposite region opposite to the first electrode via an insulating layer, and a transfer control electrode that is opposite to the first electrode and the charge storage electrode via the insulating layer, and the photoelectric conversion layer is disposed above at least the charge storage electrode via the insulating layer.