A semiconductor device according to the present disclosure includes: a first charge accumulation unit capable of accumulating a charge; a first initialization unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and a first voltage switching unit that is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit.

It is possible to curb noise, color mixing, and the like. An imaging apparatus includes: a semiconductor; a photoelectric conversion unit that is provided on the semiconductor substrate and generates electrical charge in accordance with the amount of received light through photoelectric conversion; an electrical charge holding unit that is disposed on a side closer to a first surface of the semiconductor substrate than the photoelectric conversion unit and holds the electrical charge transferred from the photoelectric conversion unit; an electrical charge transfer unit that transfers the electrical charge from the photoelectric conversion unit to the electrical charge holding unit; a vertical electrode that transmits the electrical charge generated by the photoelectric conversion unit to the electrical charge transfer unit and is disposed in a depth direction of the semiconductor substrate, and a first light control unit that is disposed on a side closer to a second surface that is a side opposite to the first surface of the semiconductor substrate than the vertical electrode, is disposed at a position overlapping the vertical electrode in a plan view of the semiconductor substrate from a normal line direction of the first surface, and has a T-shaped section in the depth direction of the substrate. The first light control member includes a first light control portion and a second light control portion extending in mutually intersecting directions in an integrated structure.

Provided is an imaging device capable of efficiently dissipating heat from an imaging element. An imaging device 100 includes: an imaging element substrate 4 on which an insulating layer 51 and a conductor layer 52 are stacked and an imaging element 41 is mounted; and a housing 1 that accommodates the imaging element substrate 4. The surface of the imaging element substrate 4 has a mounting region 45 on which an electronic component 43 including the imaging element 41 is mounted, a covered region 46 in which the conductor layer 52 is covered with the insulating layer 51, and an exposed region 47 in which the conductor layer 52 is exposed from the insulating layer 51, and the exposed region 47 is connected to the housing 1.

A single photon counting sensor array includes one or more emitters configured to emit a plurality of pulses of energy, and a detector array comprising a plurality of pixels. Each pixel includes one or more detectors, a plurality of which are configured to receive reflected pulses of energy that were emitted by the one or more emitters. A mask material is positioned to cover some but not all of the detectors of the plurality of pixels to yield blocked pixels and unblocked pixels so that each blocked pixel is prevented from detecting the reflected pulses of energy and therefore only detects intrinsic noise.

The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates. The semiconductor device includes a first semiconductor substrate, a second semiconductor substrate providing a function different from a function provided by the first semiconductor substrate, and a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate, wherein at least two semiconductor substrates are stacked and the semiconductor substrates are electrically connected to each other, and the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film inserted between an interface of the first semiconductor substrate and an interface of the second semiconductor substrate.

A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

A combination structure includes an in-plane pattern of unit cells, wherein the each unit cell includes nanostructures each having a dimension that is smaller than a near-infrared wavelength and a light-absorbing layer adjacent to the nanostructures and including a near-infrared absorbing material configured to absorb light in at least a portion of a near-infrared wavelength spectrum. The nanostructures are define a nanostructure array in the unit cells, and a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the combination structure is wider than a wavelength width at 50% transmittance of a transmission spectrum in the near-infrared wavelength spectrum of the nanostructure array.

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

In one example, an apparatus comprises: a first sensor layer, including an array of pixel cells configured to generate pixel data; and one or more semiconductor layers located beneath the first sensor layer with the one or more semiconductor layers being electrically connected to the first sensor layer via interconnects. The one or more semiconductor layers comprises on-chip compute circuits configured to receive the pixel data via the interconnects and process the pixel data, the on-chip compute circuits comprising: a machine learning (ML) model accelerator configured to implement a convolutional neural network (CNN) model to process the pixel data; a first memory to store coefficients of the CNN model and instruction codes; a second memory to store the pixel data of a frame; and a controller configured to execute the codes to control operations of the ML model accelerator, the first memory, and the second memory.

There is provided a light-detecting device. A light-detecting device includes a first substrate including a first electrode, a semiconductor layer, a first insulating film, and a via, and a second substrate that faces the first substrate and is electrically connected to the semiconductor layer through the via. The semiconductor layer includes a compound semiconductor material. The first electrode includes a first portion and the second portion. The first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with both the first insulating film and the via.