H01L27/14634

CHIP PACKAGE AND METHOD FOR FORMING THE SAME
20230238408 · 2023-07-27 ·

A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.

SEMICONDUCTOR ELEMENT
20230024598 · 2023-01-26 ·

Provided is a semiconductor element capable of inspecting a plurality of wires formed in parallel. A semiconductor element according to an embodiment includes: a first circuit (45B) connected to a first position of each of a plurality of wires of a first wire group (31) including the plurality of wires; a second circuit (45A) connected to a second position corresponding to an end of each of the plurality of wires; and a plurality of connection units (43) that connects a third circuit (14) with each of the plurality of wires, the plurality of connection units (43) being provided on a one-to-one basis to the plurality of wires between the first position and the second position of each of the plurality of wires.

IMAGING ELEMENT, ENDOSCOPE, ENDOSCOPE SYSTEM, AND TESTING METHOD
20230024742 · 2023-01-26 · ·

An imaging element includes: a pixel board including a light receiver including plural pixels, each pixel being configured to generate an imaging signal; a circuit board including a functional circuit, the pixel board being layered on the circuit board; plural wiring portions configured to electrically connect the pixel board and the circuit board to each other and electrically transmit signals between respective layers; a terminal provided on the circuit board, the terminal being electrically connected to each of the plural wiring portions, the terminal being configured to output the imaging signal to an outside of the terminal or receive an external signal from the outside of the terminal; and a switch configured to output, by selective switching, at least one of the imaging signal and an internal signal generated at the circuit board, to the terminal.

Integrating optical elements with electro-optical sensors via direct-bond hybridization

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

IMAGE SENSING DEVICE
20230026792 · 2023-01-26 ·

An image sensing device includes a first substrate layer including a photoelectric conversion region for converting incident light into photocharges and a floating diffusion region for storing the photocharges therein, a first interconnect layer disposed over the first substrate layer and including a switch transistor gate overlapping at least a portion of the floating diffusion region, a second substrate layer disposed over the first interconnect layer, a second interconnect layer disposed over the second substrate layer, and a capacitor electrically coupled to the floating diffusion region by the switch transistor gate. The capacitor includes first and second electrodes that are disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer are disposed between the first electrode and the second electrode.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first dielectric structure, a second dielectric structure, a first substrate between the first dielectric structure and the second dielectric structure, a passivation structure over the second dielectric structure, a first metallic structure over the first dielectric structure, a second metallic structure over the passivation structure, and a third metallic structure in the first and second dielectric structures, the first substrate, and the passivation structure. The second dielectric structure is between the passivation structure and the first substrate. The first metallic structure is electrically connected to the second metallic structure through the third metallic structure, the third metallic structure includes a first portion in the first dielectric structure and the first substrate, a second portion in the second dielectric structure and a third portion in the passivation structure. Widths of the first portion, the second portion and the third portion are different from each other.

UNIFORM TRENCHES IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF
20230230993 · 2023-07-20 ·

The present disclosure describes a semiconductor device having radiation-sensing regions separated by trench isolation structures. The semiconductor structure includes a first trench fill structure on a substrate and a second trench fill structure on the substrate. The first trench fill structure has a first width and a convex bottom surface. The second trench fill structure has a concave bottom surface and a second width greater than the first width.

Electromagnetic wave processing device

The present technology relates to an electromagnetic wave processing device that enables reduction of color mixture. Provided are a photoelectric conversion element formed in a silicon substrate, a narrow band filter stacked on a light incident surface side of the photoelectric conversion element and configured to transmit an electromagnetic wave having a desired wavelength, and interlayer films respectively formed above and below the narrow band filter, and the photoelectric conversion element is formed at a depth from an interface of the silicon substrate, the depth where a transmission wavelength of the narrow band filter is most absorbed. The depth of the photoelectric conversion element from the silicon substrate becomes deeper as the transmission wavelength of the narrow band filter is longer. The present technology can be applied to an imaging element or a sensor using a plasmon filter or a Fabry-Perot interferometer.

ELECTRONIC APPARATUS, METHOD FOR CONTROLLING ELECTRONIC APPARATUS, AND CONTROL PROGRAM

To generate multiple types of images of the same subject, an electronic apparatus includes a drive control unit that controls the drive of an image sensor, a division unit that divides an image capture region of the image sensor into at least first and second regions, and an image generation unit that generates a first image by capturing an image of the same subject in the first region and generates a second image by capturing an image of the same subject in the second region.

Solid-state imaging apparatus, method for manufacturing solid-state imaging apparatus, and electronic equipment equipped with solid-state imaging apparatus

Provided are a solid-state imaging apparatus, a method for manufacturing a solid-state imaging apparatus, and an electronic apparatus equipped with a solid-state imaging apparatus that can reduce the size of a semiconductor chip in such a way that one semiconductor substrate having a logic circuit controls two sensors. Provided is a solid-state imaging apparatus including a first sensor, a first semiconductor substrate having a memory, a second semiconductor substrate having a logic circuit, and a second sensor, in which the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.