A photoelectric conversion apparatus includes first and second photoelectric conversion circuits, an FD configured to hold signal charges, a first transfer transistor configured to control transfer of the signal charge from the first photoelectric conversion circuit to the FD, a second transfer transistor configured to control transfer of the signal charge from the second photoelectric conversion circuit to the FD, a first capacitor circuit configured to hold a signal charge overflowing from the first photoelectric conversion circuit, and a second capacitor circuit configured to hold a signal charge overflowing from the second photoelectric conversion circuit. The first capacitor circuit is connected to a capacitance addition transistor via a first capacitor-connected transistor. The second capacitor circuit is connected to the capacitance addition transistor via a second capacitor-connected transistor. The first and second capacitor-connected transistors are connected to the FD via the capacitance addition transistor.

A solid-state imaging element includes a pixel including a first imaging element, a second imaging element, a third imaging element, and an on-chip micro lens 90. The first imaging element includes a first electrode 11, a third electrode 12, and a second electrode 16. The pixel further includes a third electrode control line VOA connected to the third electrode 12 and a plurality of control lines 62B connected to various transistors included in the second and third imaging elements and different from the third electrode control line VOA. In the pixel, a distance between the center of the on-chip micro lens 90 included in the pixel and any one of the plurality of control lines 62B included in the pixel is shorter than a distance between the center of the on-chip micro lens 90 included in the pixel and the third electrode control line VOA included in the pixel.

An image sensor includes a semiconductor substrate including a first surface and a second surface and having a photoelectric conversion region disposed therein. A floating diffusion region is disposed within the semiconductor substrate. The floating diffusion region is adjacent to the first surface. A buried gate structure is disposed within a buried gate trench extending from the first surface of the semiconductor substrate towards an interior of the semiconductor substrate, the buried gate structure including a first buried gate electrode inside a first buried gate trench adjacent to a first side part of the floating diffusion region, and a second buried gate electrode inside a second buried gate trench spaced apart from the first buried gate trench and adjacent to a second side part of the floating diffusion region, the second side part being opposite to the first side part.

An image sensor includes a pixel division structure, a light sensing element, a transistor, a color filter array layer, and a microlens. The pixel division structure extends through a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, and defines unit pixel regions in which unit pixels are respectively formed. The light sensing element is formed in each of the unit pixel regions. The transistor is formed on the substrate. The color filter array layer is formed under the substrate, and includes color filters. The microlens is formed under the color filter array layer. The transistor includes a gate structure on an active fin protruding from the upper surface of the substrate and source/drain regions at portions of the active fin adjacent to the gate structure.

There is provided a solid state image sensor including a photoelectric conversion unit formed and embedded in a semiconductor substrate, an impurity region that retains an electric charge generated by the photoelectric conversion unit, and a transfer transistor that transfers the electric charge to the impurity region. A gate electrode of the transfer transistor is formed in a depth direction toward the photoelectric conversion unit in the semiconductor substrate, from a surface of the semiconductor substrate on which the impurity region is formed. A channel portion of the transfer transistor is surrounded by the gate electrode in two or more directions other than a direction of the impurity region, as seen from the depth direction.

An image sensor includes a first semiconductor substrate, a photoelectric conversion region in the first semiconductor substrate, and a buried insulating film on the first semiconductor substrate. The buried insulating film covers a first region of the first semiconductor substrate and exposes a second region of the first semiconductor substrate. The sensor includes a second semiconductor substrate on the buried insulating film, an operating gate structure defining a first channel of a first conductive type in the second semiconductor substrate, and a transfer gate structure defining a second channel of a second conductive type different from the first conductive type in the second region of the first semiconductor substrate.

An image sensor may include a plurality of pixels. At least some of the pixels may each include a photodiode having a charge accumulation region (“PD”), a floating diffusion region (“FD”), and a vertical gate transfer (“GT”). The GT may include one or more charge transfer regions formed vertically between PD and FD. The GT may also include a gate control region (“gate”) that may be formed in a vertical trench and be disposed laterally proximate the one or more charge transfer regions of the GT. By applying a control signal to the gate, the GT may selectively transfer at least some charge accumulated in PD to FD vertically through the one or more charge transfer regions of GT between PD and FD.

An image sensor may include a lower device on a lower substrate, an intermediate device on an intermediate substrate on the lower substrate, and an upper device on an upper substrate on the intermediate substrate. The lower device may include a logic transistor. The intermediate device may include at least one transistor. The upper device may include a photodiode and a floating diffusion region. The lower substrate, the intermediate substrate and the upper substrate may be stacked. The intermediate substrate may include a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern. An insulation pattern fills an opening at least partially defined by one or more inner surfaces of the first semiconductor layer. A buried insulation pattern fills a trench extending through the second semiconductor layer pattern.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

A pixel in an image sensor can include a photodetector and a storage region disposed in one substrate, or a photodetector disposed in one substrate and a storage region in another substrate. A buried light shield is disposed between the photodetector and the storage region. A sense region, such as a floating diffusion, can be adjacent to the storage region, with the buried light shield disposed between the photodetector and the storage and sense regions. When the photodetector and the storage region are disposed in separate substrates, a vertical gate can be formed through the buried light shield and used to initiate the transfer of charge from the photodetector and the storage region. A transfer channel formed adjacent to, or around the vertical gate provides a channel for the charge to transfer from the photodetector to the storage region.