Provided are an image sensor and an imaging apparatus. The image sensor of a multi-layered sensor structure, the image sensor includes a plurality of sensing pixels, each of the plurality of sensing pixels including a micro lens configured to collect light, a first photoelectric converter configured to convert light of a first wavelength band into an electric signal, and a second photoelectric converter formed on a substrate configured to convert incident light into the electric signal, wherein a central axis of the second photoelectric converter is spaced apart from an optical axis of the micro lens.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

An imaging element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer including a p-type semiconductor and an n-type semiconductor, and provided between the first electrode and the second electrode, in which the photoelectric conversion layer has an exciton charge separation rate of 1×10.sup.10 s.sup.−1 to 1×10.sup.16 s.sup.−1 both inclusive in a p-n junction surface formed by the p-type semiconductor and the n-type semiconductors.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a photodetector disposed within a substrate. A grid structure is disposed over the substrate and the photodetector. A conductive layer is disposed between the grid structure and the substrate. A conductive contact extends into an upper surface of the substrate. The conductive layer is directly electrically coupled to the conductive contact.

An image pickup element 10 includes a first electrode 21, a charge accumulation electrode 24 that is arranged apart from the first electrode 21, a photoelectric conversion unit 23 that contacts the first electrode 21 and is formed above the charge accumulation electrode 24 via an insulation layer 82, and a second electrode 22 formed on the photoelectric conversion unit 23. The photoelectric conversion unit 23 includes, from the second-electrode side, a photoelectric conversion layer 23A, and an inorganic oxide semiconductor material layer 23B including In.sub.aGa.sub.bSn.sub.cO.sub.d, and 0.30≤b/(a+b+c)≤0.50 and b≥c are satisfied.

A solid-state image sensor includes pixel cells each of which is formed in and above a semiconductor substrate and that are arranged in each of a first direction and a second direction intersecting the first direction to form a two-dimensional array. The pixel cells include a first pixel cell and a second pixel cell arranged in the second direction, and the pixel circuit of the first pixel cell and the pixel circuit of the second pixel cell are adjacent to each other in the second direction between the photodetection portion of the first pixel cell and the photodetection portion of the second pixel cell. Each of the first transistors of the first pixel cell shares a gate electrode with the first transistor of the second pixel cell that has the same function as the first transistor of the first pixel cell.

Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

A solid-state imaging device includes a plurality of photoelectric converting units and a plurality of charge-accumulating units each accumulating a charge generated in the corresponding photoelectric converting unit. The photoelectric converting unit includes a photosensitive region that generates the charge in accordance with light incidence, and an electric potential gradient forming unit that accelerates migration of charge in a second direction in the photosensitive region. The charge-accumulating unit includes: a plurality of regions (semiconductor layers) having an impurity concentration gradually changed in one way in the second direction, and electrodes adapted to apply electric fields to the plurality of regions. Each of the electrodes is disposed over the plurality of regions having the impurity concentration gradually varied.

A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

The present disclosure relates to a solid-state imaging device, an electronic apparatus, and a manufacturing method that are designed to further increase conversion efficiency. A solid-state imaging device includes a pixel in which element separation is realized by a first trench element separation region having a trench structure in a region between an FD unit and an amplifying transistor among element separation elements separating the elements constituting the pixel from one another, and a second trench element separation region having a trench structure in a region other than the region between the FD unit and the amplifying transistor among the element separation regions separating the elements constituting the pixel from one another, and the first trench element separation region is deeper than the second trench element separation region. The present technology can be applied to CMOS image sensors, for example.