Patent classifications
H01L27/14654
Image sensor having pickup region
The present invention provides an image sensor. An image sensor include a pixel array. The pixel array includes: a plurality of pixels; and an isolation structure suitable for insulating between the plurality of pixels. The isolation structure includes: a first conductivity-type conductive layer formed over a substrate; and a second conductivity-type pickup region formed in the first conductivity-type conductive layer and disposed between each plurality of pixels.
Shared pixel and an image sensor including the same
A shared pixel includes a plurality of photo diode regions, a shared floating diffusion region, a plurality of transfer gates and a blooming layer. Each of the photo diode regions generates photo-charges in response to incident light. The photo diode regions are formed in a semiconductor substrate. The shared floating diffusion region is shared by the plurality of photo diode regions. The shared floating diffusion region is separated from the plurality of photo diode regions in the semiconductor substrate. Each of the transfer gates transfers the photo-charges of a corresponding photo diode region to the shared floating diffusion region in response to a transfer control signal. The blooming layer transfers overflow photo-charges to a power supply voltage node.
Phase detection pixels with high speed readout
Phase detection pixel pairs may include first and second photodiodes covered by a single microlens. To decrease the readout time of the phase detection pixels, each phase detection pixel may have a respective floating diffusion region. Each phase detection pixel may include a transfer gate that can be asserted to transfer charge from the photodiode to the floating diffusion region. During readout, charge from each photodiode in the phase detection pixel pair may be read out in parallel. The phase detection pixel pairs may be implemented in multiple substrates connected by interconnect layers.
Image sensor with anti-blooming gate
The invention concerns active-pixel electronic image sensors. The pixel comprises a photodiode (PH) designed in a semiconductor active layer (12) and maintained at a nil reference potential, and above the active layer an anti-blooming gate (G5) adjacent on one side to the photodiode and on another side to an evacuation drain (22). The sensor comprises means for applying to the anti-blooming gate, during most of the duration of integration, a blocking potential creating beneath the gate a potential barrier of a first height, and, during a series of brief pulses over the duration of integration, an anti-blooming potential creating a potential barrier of a second height, lower than the first. The fact of only applying the anti-blooming voltage during the brief pulses reduces the dark noise induced by tunneling effect by the electric field between gate and photodiode.
PHASE DETECTION PIXELS WITH HIGH SPEED READOUT
Phase detection pixel pairs may include first and second photodiodes covered by a single microlens. To decrease the readout time of the phase detection pixels, each phase detection pixel may have a respective floating diffusion region. Each phase detection pixel may include a transfer gate that can be asserted to transfer charge from the photodiode to the floating diffusion region. During readout, charge from each photodiode in the phase detection pixel pair may be read out in parallel. The phase detection pixel pairs may be implemented in multiple substrates connected by interconnect layers.
IMAGE SENSORS WITH HYBRID THREE-DIMENSIONAL IMAGING
Image sensors may include hybrid three-dimensional imaging pixel groups. The pixel groups may be capable of obtaining both phase detection information and time-of-flight information. A pixel group may have first and second photodiodes covered by a single microlens that are used to obtain phase detection information. The microlens may also cover a third photodiode that obtains time-of-flight information. The first and second photodiodes may be formed in a first substrate whereas the third photodiode may be formed in a second substrate. The first and second substrates may be connected by a metal interconnect layer.
Method for avoiding pixel saturation
The invention relates to a method for avoiding pixel saturation in a group of pixels, each having a node, wherein a reference voltage is predetermined, and wherein a voltage change at the node of only one of the pixels compared to the predetermined reference voltage causes the synchronous reset of all pixels of the group.
IMAGE SENSORS
An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region. The second potential level is greater than the first potential level.
Vertically stacked image sensor
A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
Apparatus and methods for buried channel transfer gate
An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. A buried channel may be formed under the transfer gate. The buried channel may extend from the floating diffusion to overlap a portion of the transfer gate without extending completely beneath the transfer gate or reaching the photodiode. The buried channel may provide a path for antiblooming current from the photodiode to reach the floating diffusion, while allowing for the transfer gate off voltage to remain high enough to prevent transfer gate dark current from flowing into the photodiode.