The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates. The semiconductor device includes a first semiconductor substrate, a second semiconductor substrate providing a function different from a function provided by the first semiconductor substrate, and a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate, wherein at least two semiconductor substrates are stacked and the semiconductor substrates are electrically connected to each other, and the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film inserted between an interface of the first semiconductor substrate and an interface of the second semiconductor substrate.

A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

There is provided a light-detecting device. A light-detecting device includes a first substrate including a first electrode, a semiconductor layer, a first insulating film, and a via, and a second substrate that faces the first substrate and is electrically connected to the semiconductor layer through the via. The semiconductor layer includes a compound semiconductor material. The first electrode includes a first portion and the second portion. The first portion of the first electrode is in contact with the semiconductor layer, and the second portion is in contact with both the first insulating film and the via.

A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

A semiconductor device includes a first dielectric structure, a second dielectric structure, a first substrate between the first dielectric structure and the second dielectric structure, a passivation structure over the second dielectric structure, a first metallic structure over the first dielectric structure, a second metallic structure over the passivation structure, and a third metallic structure in the first and second dielectric structures, the first substrate, and the passivation structure. The second dielectric structure is between the passivation structure and the first substrate. The first metallic structure is electrically connected to the second metallic structure through the third metallic structure, the third metallic structure includes a first portion in the first dielectric structure and the first substrate, a second portion in the second dielectric structure and a third portion in the passivation structure. Widths of the first portion, the second portion and the third portion are different from each other.

Provided are a solid-state imaging apparatus, a method for manufacturing a solid-state imaging apparatus, and an electronic apparatus equipped with a solid-state imaging apparatus that can reduce the size of a semiconductor chip in such a way that one semiconductor substrate having a logic circuit controls two sensors. Provided is a solid-state imaging apparatus including a first sensor, a first semiconductor substrate having a memory, a second semiconductor substrate having a logic circuit, and a second sensor, in which the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.

A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

A camera module and array camera module with circuit board unit and photosensitive unit and manufacturing method thereof is provided. The array camera module includes two or more camera lenses and a circuit unit. The circuit unit includes a circuit board portion for electrically connecting two or more photosensitive sensors of the array camera module, and a conjoined encapsulation portion integrally encapsulated on the circuit board portion. The camera lenses are respectively arranged along the photosensitive paths of the photosensitive sensors.

There is provided an imaging device including: a first semiconductor substrate having a first region that includes a photoelectric conversion section and a via portion, a second region adjacent to the first region, a connection portion disposed at the second region, and a second semiconductor substrate, wherein the connection portion electrically couples the first semiconductor substrate to the second semiconductor substrate in a stacked configuration, and wherein a width of the connection portion is greater than a width of the via portion.

The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.