Provided is an imaging unit that includes two or more imaging devices that are different from each other in imaging direction, and a substrate formed with each of the imaging devices. The substrate has a coupler formed between the imaging devices. The imaging unit including the plurality of imaging devices is able to yield a high-quality image when capturing an image of a wide range.

A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.

An image sensor includes a substrate having first and second surfaces and first and second regions. Unit pixels including photoelectric conversion layers are arranged inside the first region. A pixel separation pattern extends from the first surface to the second surface in the first region, separates each of the unit pixels, and includes a pixel separation spacer film and a pixel separation filling film. A dummy pixel separation pattern extends from the first surface to the second surface in the second region, and includes a dummy pixel separation filling film. A wiring structure disposed on the second surface includes an inter-wiring insulating film and a first wiring. A first contact directly connects the dummy pixel separation filling film and connects the dummy pixel separation filling film to the first wiring. A height of the pixel separation filling film is greater than a height of the dummy pixel separation filling film.

Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.

The technology of this application relates to a semiconductor device that may include a first wafer, a second wafer, and a contact plug. The first wafer may include a first dielectric layer, and the first dielectric layer has a first connection pad. The second wafer is bonded to the first wafer, the second wafer includes a second dielectric layer, and the second dielectric layer has a second connection pad. The contact plug is made of a conductive material filled in a vertical through hole, and is configured to electrically connect the first connection pad and the second connection pad. The vertical through hole is a through hole that is formed through etching and that passes through the first wafer and partially passes through the second wafer to an upper surface and/or a sidewall of the second connection pad.

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

In order to enable simple removal of a substrate used for manufacturing a semiconductor element, a manufacturing method includes forming a graphene layer on a substrate portion formed of a semiconductor, forming an element portion on the graphene layer, the element portion including a semiconductor layer directly formed on the graphene layer, which takes over crystal information relating to the substrate portion when the semiconductor layer is formed on the substrate portion without intermediation of the graphene layer, and performing cutting-off between the substrate portion and the element portion at the graphene layer.

A method of manufacturing a photodetection device, the method includes preparing a light-receiving element including a first main surface including an arrangement of a plurality of first electrodes, forming a first bump containing In on each of the plurality of first electrodes, preparing a circuit substrate including a second main surface including an arrangement of a plurality of second electrodes, forming a second bump containing In on each of the plurality of second electrodes, forming, at at least one of a surface of the first bump or a surface of the second bump, a first oxide film containing In, placing the first main surface and the second main surface so as to face each other, and placing the first bump and the second bump on top of each other with the first oxide film therebetween.

The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.

Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer.