A packaging unit, a component packaging structure and a preparation method thereof. The packaging unit includes a bonding substrate and spacers formed on the bonding substrate through a patterning process, wherein the bonding substrate is reserved with packaging regions for applying sealant. When the packaging unit is used to package a component, because the spacer(s) is supported between the bonding substrate and the base substrate, the packaging unit is easy to separate from the base substrate At the same time, the packaging unit has little or no damage to the base substrate and elements formed on the base substrate, thus effectively protecting the performance of the base substrate and the elements on the base substrate.

A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.

Provided is a semiconductor device that includes a semiconductor layer, a channel region, first and second main electrode regions, a gate insulating film, and a gate electrode. The first and second main electrode regions are on opposing ends of the channel region. The gate insulating film is disposed on the inner walls of first and second trenches and on the upper surface of the channel region. The gate electrode includes a first protruding section, a second protruding section, and a horizontal section. The first protruding section and the second protruding section are embedded in first and second trenches respectively. The horizontal section is connected to the upper ends of the first and second protruding sections and disposed on the upper surface of the channel region. The depth of the first and second main electrode regions is equal to or greater than the depth of the first and second protruding sections.

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a dopant having a first doping type. A deep well region is disposed within the semiconductor substrate, where the deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type, where the second dopant comprises gallium.

An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (μLED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

A method includes forming a package, which includes an optical die and a protection layer attached to the optical die. The optical die includes a micro lens, with the protection layer and the micro lens being on a same side of the optical die. The method further includes encapsulating the package in an encapsulant, planarizing the encapsulant to reveal the protection layer, and removing the protection layer to form a recess in the encapsulant. The optical die is underlying the recess, with the micro lens facing the recess.

The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.