An imaging device includes a semiconductor substrate, pixels, a charge detector, charge storage portions, an output gate portion and a shift gate portion. The pixels and the charge detector are provided in the semiconductor substrate. The charge storage portions are provided on the charge detector side of the pixels, and linked to the pixels. The output gate portion is positioned between the charge detector and the charge storage portions, and includes charge transfer channels extending in a radial configuration in directions from the charge detector toward the pixels. The shift gate portion is positioned between one charge storage portion and one charge transfer channel. The shift gate portion includes a gate electrode provided on the semiconductor substrate. A planar configuration of the gate electrode has a side orthogonal to the extending direction of the one charge transfer channels, the side being most proximal to the one charge transfer channel.

An optoelectronic module operable to acquire distance data and spectral data includes an array of demodulation pixels and an array of spectral filters. The demodulation pixels can possess an intrinsic wavelength-dependent sensitivity, wherein the intrinsic wavelength-dependent sensitivity can be offset by an intensity balancing micro-lens array in some cases. In some cases, the intrinsic wavelength-dependent sensitivity can be offset by a combined filter array, while in other cases the intrinsic wavelength-dependent sensitivity can be offset by an intensity balancing filter array. Still in other cases, the demodulation pixels can be operable in such as to offset the intrinsic wavelength-dependent sensitivity.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.

An optical detection unit AR is divided so as to have a plurality of pixel regions PX aligned in a column direction. Signals from the plurality of pixel regions PX are integrated for each optical detection unit AR, and output the signal as an electrical signal corresponding to a one-dimensional optical image in time series. Each of the pixel regions PX includes a resistive gate electrode R which promotes transfer of charges in the photoelectric conversion region and a charge accumulation region S2. A drain region ARD is adjacent to the charge accumulation region S2 through a channel region.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

An optoelectronic module operable to acquire distance data and spectral data includes an array of demodulation pixels and an array of spectral filters. The demodulation pixels can possess an intrinsic wavelength-dependent sensitivity, wherein the intrinsic wavelength-dependent sensitivity can be offset by an intensity balancing micro-lens array in some cases. In some cases, the intrinsic wavelength-dependent sensitivity can be offset by a combined filter array, while in other cases the intrinsic wavelength-dependent sensitivity can be offset by an intensity balancing filter array. Still in other cases, the demodulation pixels can be operable in such as to offset the intrinsic wavelength-dependent sensitivity.

Provided herein include various examples of an apparatus, flow cells that include these examples of the apparatus, and methods of making these examples of the apparatus. The apparatus can include a molding layer over a substrate and covering sides of a light detection device. The molding layer comprises a first region and a second region, which, with the active surface of the light detection device, form a contiguous surface. A waveguide integration layer is between the contiguous surface and a waveguide. The waveguide integration layer comprises optical coupling structures over the first and second regions, to optically couple light waves from a light source to the waveguide. The waveguide utilizes the light waves to excite light sensitive materials in nanowells. A nanostructure layer over the waveguide comprises the nanowells. Each nanowell shares a vertical axis with a location on the active surface of the light detection device.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.