A pixel group of an image sensor includes first through fourth unit pixels in a matrix form of two pixels rows and two pixel columns, and a common floating diffusion region in a semiconductor substrate at a center of the pixel group and shared by the first through fourth unit pixels. Each of the first through fourth unit pixels includes a photoelectric conversion element in the semiconductor substrate, and a pair of vertical transfer gates in the semiconductor substrate and extending in a vertical direction perpendicular to a surface of the semiconductor substrate. The pair of vertical transfer gates transfer photo charges collected by the photoelectric conversion element to the common floating diffusion region. Image quality is enhanced by increasing sensing sensitivity of the unit pixel through the shared structure of the floating diffusion region and the symmetric structure of the vertical transfer gates.

An image sensor includes an image sensor pixel array having pixels. Each pixel includes a continuous active region having a first portion and a second portion extending from the first portion. A photodiode, a reset transistor, a drive transistor, and a select transistor are formed in and over the first portion. The photodiode and the reset transistor define a floating diffusion region therebetween. A switch transistor is formed in and over the second portion and includes a first source/drain region and a second source/drain region. The first source/drain region is included in the floating diffusion region. The second source/drain region interfaces a doped region formed in the second region. The pixel also includes a gate structure disposed directly over the doped region. By controlling the switch transistor, the pixel may operate in a high conversion gain mode or a low conversion gain mode to accommodate different illumination or exposure conditions.

An image sensor includes a pixel array including a plurality of pixel groups, each of the plurality of pixel groups including a plurality of unit pixels and sharing a single microlens, the plurality of unit pixels in each of the plurality of pixel groups including color filters of the same color, and a control logic configured to group the plurality of unit pixels of each of the plurality of pixel groups into a plurality of subgroups and to drive the pixel array for each subgroup. The plurality of subgroups include a first subgroup and a second subgroup. The control logic may be configured to obtain first image data corresponding to the first subgroup and second image data corresponding to the second subgroup, and the first subgroup and the second subgroup are provided with at least one unit pixel therebetween in the first direction or the second direction.

There is provided a pixel circuit including a first circuit and a second circuit. The first circuit is used to output a first voltage associated with exposure intensity. The second circuit is used to output a second voltage associated with exposure time interval. The processor multiples the first voltage to a ratio between a reference voltage and the second voltage to obtain an actual light intensity, wherein the reference voltage is a voltage value outputted by the second circuit of a dummy pixel.

An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.

The present disclosure relates to an optical amplifier configured for an image capturing device. The optical amplifier may include a substrate. The optical amplifier may also include an optical amplification region formed over the substrate. The optical amplification region may include a first optical amplification layer and a second optical amplification layer. The first optical amplification layer may be configured to amplify light at a first wavelength range, and the second optical amplification layer may be configured to amplify light at a second wavelength range. The optical amplifier may further include at least one electrode layer electrically contacting the optical amplification region.

A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

The present disclosure relates to a solid-state imaging device capable of receiving light entering a gap between pixel regions of imaging units by the pixel region when a plurality of imaging units is arranged, a method of manufacturing the same, and an electronic device. A CMOS image sensor includes a pixel region formed of a plurality of pixels. A convex lens is provided for each of a plurality of CMOS image sensors. A plurality of CMOS image sensors is arranged on a supporting substrate. The present disclosure is applicable to a solid-state imaging device and the like in which a plurality of CMOS image sensors is arranged on the supporting substrate, for example.

An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor material between the photodiode and the storage diode. Further, the buried storage well may be disposed under the storage diode and partially under the transfer storage gate. Additionally, a length of the transfer storage gate and a length of the storage diode may be equal, and the storage diode may passivate a surface of the semiconductor material between the transfer storage gate and an output gate.

An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.