An image sensing device includes a first subpixel block, a second subpixel block, a first conversion gain transistor, and a second conversion gain transistor. The first subpixel block includes a first floating diffusion region and a plurality of unit pixels sharing the first floating diffusion region. The second subpixel block includes a second floating diffusion region coupled to the first floating diffusion region and a plurality of unit pixels sharing the second floating diffusion region. The first conversion gain transistor includes a first impurity region coupled to the first and second floating diffusion regions and a second impurity region coupled to a first conversion gain capacitor. The second conversion gain transistor includes a third impurity region coupled to the second impurity region of the first conversion gain transistor and a fourth impurity region coupled to a second conversion gain capacitor.

A solid-state imaging device according to an embodiment of the present disclosure includes a mode-switching switch section that, in a first mode, electrically couples a first signal path to a photoelectric conversion section and electrically decouples a second signal path from the photoelectric conversion section, and that, in a second mode, electrically couples both of the first signal path and the second signal path to the photoelectric conversion section. At least the photoelectric conversion section is formed in a first substrate, and at least a second amplification transistor is formed in a second substrate, among the first substrate and the second substrate stacked on each other.

An image sensor is provided. The image sensor includes a pixel array in which a plurality of pixels are arranged, wherein each of the plurality of pixels includes a photodiode; a floating diffusion node configured to integrate photocharges generated in the photodiode; a first sampling transistor electrically connected to a first node; a first capacitor electrically connected to a first node and configured to store a charge corresponding to a voltage of the floating diffusion node which is reset; a second sampling transistor electrically connected to a second node; a second capacitor electrically connected to the second node and configured to store a charge corresponding to a voltage of the floating diffusion node in which the photocharges are integrated; and at least one mode transistor configured to adjust an equivalent capacitance of each of the first node and the second node according to a mode control signal.

An image sensor includes a substrate having a first surface and a second surface, which are opposite to each other, the substrate including a unit pixel region including a device isolation pattern adjacent to the first surface and a photoelectric conversion region adjacent to the second surface, a pixel isolation pattern provided in the substrate to define the unit pixel regions, an impurity region in the unit pixel region and being adjacent to a side surface of the device isolation pattern, a gate electrode provided on the first surface, and an auxiliary isolation pattern provided between a first side surface of the gate electrode and the impurity region, when the image sensor is viewed in a plan view. A bottom surface of the auxiliary isolation pattern may be located at a level different from a bottom surface of the device isolation pattern.

A solid-state image sensing device is of a global-shutter type and includes a vertical driving unit and an analog-to-digital (AD) converter. The vertical driving unit performs a shutter operation during a time period from when the AD converter starts an AD conversion to when the AD converter ends the AD conversion. The AD converter does not output a digital signal during a time period from when the vertical driving unit starts the shutter operation to when the vertical driving unit ends the shutter operation.

An image sensing device may include: a plurality of pixels included in a first row; a first signal line configured to transfer a boosting voltage to the plurality of pixels; a first switch transistor coupled between the first signal line and a second signal line disposed adjacent to the top side of the first signal line; and a second switch transistor coupled between the first signal line and a third signal line disposed adjacent to the bottom side of the first signal line.

A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

A first region includes a plurality of first transfer column regions distributed in a first direction. A second region includes a plurality of second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction in the second transfer section. Lengths in a second direction of the plurality of first transfer column regions are equal. Lengths in the second direction of the plurality of second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region in the second direction increases in the charge transfer direction in response to a change in the lengths of the plurality of second transfer column regions.

A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

A first region includes first transfer column regions distributed in a first direction. A second region includes second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction. Lengths in a second direction of the first transfer column regions are equal. Lengths in the second direction of the second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region increases in response to a change in the lengths of the second transfer column regions.