An optical sensor device may include a set of optical sensors. The optical sensor device may include a substrate. The optical sensor device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first dielectric mirror disposed on the substrate. The multispectral filter array may include a spacer disposed on the first dielectric mirror. The spacer may include a set of layers. The multispectral filter array may include a second dielectric mirror disposed on the spacer. The second dielectric mirror may be aligned with two or more sensor elements of a set of sensor elements.

An optical sensor device may include a set of optical sensors. The optical sensor device may include a substrate. The optical sensor device may include a multispectral filter array disposed on the substrate. The multispectral filter array may include a first dielectric mirror disposed on the substrate. The multispectral filter array may include a spacer disposed on the first dielectric mirror. The spacer may include a set of layers. The multispectral filter array may include a second dielectric mirror disposed on the spacer. The second dielectric mirror may be aligned with two or more sensor elements of a set of sensor elements.

An imaging system including a sensor wafer and a logic wafer. The sensor wafer includes a plurality of pixels arranged in rows and columns, the plurality of pixels arranged in rows and columns and including at least a first pixel and a second pixel positioned in a first row included in the rows. The sensor wafer includes a first transfer control line associated with the first row, the first transfer control line coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel. The logic wafer includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, a first storage control line coupled to a first storage gate associated with the first pixel and a second storage control line coupled to a second storage gate associated with the second pixel.

A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.