A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.

Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

An approach provides a metal-insulator-metal capacitor with a comb-like structure. The metal-insulator-metal capacitor includes a first electrode material forming a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal. An insulator material surrounds the first electrode metal and exposes a top surface of the central, vertical portion of the first electrode metal. The metal-insulator-metal capacitor includes a second electrode material surrounding the insulator material. The metal-insulator-metal capacitor includes a first electrode contact connecting to the top surface of the central, vertical portion of the first electrode metal and a second electrode contact connecting to a top surface of the second electrode material.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.

A capacitor structure implemented using a semiconductor process. The capacitor structure includes a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material, and a plurality of patterned metallization layers separated by the dielectric material. Each interdigitated electrode finger comprises a lateral part formed on one of at least two essentially parallel first metallization layers and a vertical part includes a plurality of superimposed slabs or bars disposed on a plurality of second metallization layers between said first metallization layers and electrically connected to each other and to the lateral part with a plurality of electrically conducting vias traversing through dielectric material separating adjacent metallization layers. Vertical distance between each pair of at least partially superimposed lateral parts of two adjacent electrode fingers is substantially equal to lateral distance between two adjacent vertical parts.

The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.