A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

A method for forming a semiconductor structure can include the following steps. A substrate and an insulating layer that are stacked are provided, the substrate having a plurality of storage node contact structures spaced apart from each other. A grid-like upper electrode layer is formed on a surface of the insulating layer, where the upper electrode layer has a plurality of meshes penetrating the upper electrode layer, and an orthographic projection of each of the meshes on the insulating layer and an orthographic projection of a storage node contact structure on the insulating layer have an overlapping area. A dielectric layer is formed on a side wall of each mesh. The insulating layer exposed from the mesh is removed to expose the storage node contact structure. A lower electrode layer is formed inside each mesh.

Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

A method for manufacturing a capacitive device comprising the following steps: a) providing a metallic layer, b) depositing a full-sheet aluminium layer, c) structuring pores in the aluminium layer by a full-sheet anodic etching process, subsequently to which a continuous porous alumina layer is obtained comprising a first main face and a second main face, longitudinal pores extending from the first main face to the second main face, d) forming a capacitive area at a first area of the porous alumina layer, e) forming an upper electrode over the capacitive area, f) forming a contact resumption at a second area of the porous alumina layer, g) forming a lower electrode over the contact resumption.

The present invention relates to a capacitor and its formation method and to a DRAM cell. In various embodiments, a substrate is provided such that an electrical contact portion is formed thereon. A dielectric layer is formed on a surface of the substrate, including alternately stacked supporting layers and sacrificial layers. At least two capacitor holes penetrating the sacrificial layers and the supporting layers can formed to expose the same electrical contact portion. A lower electrode layer covering the inner surface of the capacitor holes can be formed. The lower electrode layer is connected to the electrical contact portion. The sacrificial layers are then removed and a capacitor dielectric layer and an upper electrode layer are formed successively on the inner and outer surfaces of the lower electrode layer and on the surface of the supporting layers. This can increase capacitance value per unit area of the capacitor.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

A capacitor structure implemented using a semiconductor process. The capacitor structure includes a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material, and a plurality of patterned metallization layers separated by the dielectric material. Each interdigitated electrode finger comprises a lateral part formed on one of at least two essentially parallel first metallization layers and a vertical part includes a plurality of superimposed slabs or bars disposed on a plurality of second metallization layers between said first metallization layers and electrically connected to each other and to the lateral part with a plurality of electrically conducting vias traversing through dielectric material separating adjacent metallization layers. Vertical distance between each pair of at least partially superimposed lateral parts of two adjacent electrode fingers is substantially equal to lateral distance between two adjacent vertical parts.

Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

A method for fabricating a semiconductor device, including the steps of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing a wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole.