Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a ferroelectric layer disposed between the first electrode and the second electrode, and a recess between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of −55 degrees C. to 125 degrees C.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.

The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.

A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of −55 degrees C. to 125 degrees C.

An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.