An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.

In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.

Certain aspects of the present disclosure provide a metal-on-metal (MoM) capacitor with metal layers, each layer having two different electrical conductors with orthogonally-arranged conductive arteries and orthogonally-oriented conductive fingers. One exemplary MoM capacitor generally includes a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a first electrical conductor providing a first node of the MoM capacitor and a second electrical conductor providing a second node of the MoM capacitor. According to aspects, the first electrical conductor comprises a first plurality of conductive fingers and the second electrical conductor comprises a second plurality of conductive fingers. Further, conductive fingers of the first plurality of conductive fingers are interdigitated with conductive fingers of the second plurality of conductive fingers. Additionally, the first electrical conductor in the first metal layer is oriented orthogonal to the second electrical conductor in the first metal layer.

A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.

Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.

A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116.

An array substrate is provided. The array substrate includes a capacitor, which includes a plurality of metal electrodes arranged opposite to each other. The plurality of metal electrodes are spaced apart from each other in a horizontal direction parallel to a plane in which the array substrate is located, and an orthogonal projection of each of at least two of the plurality of metal electrodes of the capacitor on the plane in which the array substrate is located includes a curved portion.

A capacitor, an array substrate and a method for manufacturing the same, and a display panel are provided. The capacitor includes a main body including a first pole plate and a second pole plate disposed opposite to each other, and the capacitor further includes at least one auxiliary body. Any one of the at least one auxiliary body includes a third pole plate and a fourth pole plate disposed opposite to each other, and neither the third pole plate nor the fourth pole plate extends in a plane where the first pole plate is located or a plane where the second pole plate is located. The main body is connected in parallel with the at least one auxiliary body. The array substrate includes a transistor and the capacitor provided by the present disclosure, and the transistor is electrically connected to the capacitor.

A capacitor structure includes a first metal structure, a second metal structure, and a dielectric material. The second metal structure is disposed below the first metal structure. Each of the first metal structure and the second metal structure includes at least three conductive components. The conductive components have a fish-bone shape. The dielectric material is disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure.

A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose an etch stop layer in the preliminary pattern; forming a dielectric layer on a sidewall of the opening; performing a first etching process to penetrate the etching stop layer and form a hole; performing a second etching process to expand a portion of the hole in the substrate; removing the dielectric layer; and depositing a conductive preliminary pattern on the sidewall of the opening and in the hole.