The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

A semiconductor device may include a cell capacitor including first lower electrodes, a first upper support layer pattern, a first dielectric layer, and a first upper electrode. The decoupling capacitor may include second lower electrodes, a second upper support layer pattern, a second dielectric layer, and a second upper electrode. The first and second lower electrodes may be arranged in a honeycomb pattern at each vertex of a hexagon and a center of the hexagon. The first upper support layer pattern may be connected to upper sidewalls of the first lower electrodes. The first upper support layer pattern may correspond to a first plate defining first openings. The second upper support layer pattern may be connected to upper sidewalls of the second electrodes. The second upper support layer pattern may correspond to a second plate defining second openings having a shape different from a shape of the first opening.

A semiconductor device may include lower electrodes on a substrate, a first upper support layer pattern on upper sidewalls of the lower electrodes, and a dielectric layer and an upper electrode on surfaces of the lower electrodes and the first upper support layer pattern. The lower electrodes may be in a honeycomb pattern with the lower electrodes are at vertexes and center of a hexagon. The first upper support layer pattern may be a first plate shape including openings exposing some of all the lower electrodes. The lower electrodes may form rows in a first direction, the rows arranged in a second direction perpendicular to the first direction. Each opening may expose portions of upper sidewalls of at least four lower electrodes in two adjacent rows. Each of the openings may have a longitudinal direction in the first direction. In semiconductor devices, defects from bending stresses may be decreased.

Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

Some embodiments include an integrated assembly having a laterally-extending container-shaped first capacitor electrode, and having a laterally-extending container-shaped second capacitor electrode laterally offset from the first capacitor electrode. Capacitor dielectric material lines interior surfaces and exterior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends along the lined interior and exterior surfaces of the first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.

A semiconductor device includes a substrate and at least one capacitor element on each of opposite surfaces of the substrate. The at least one capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate, and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.