Patent classifications
H01L29/0669
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
A semiconductor structure includes a base and a conductive channel structure, in which the conductive channel structure includes a base and a conductive channel structure which includes a first conductive channel layer including a first conductive channel, and a first and a second doped regions respectively located at two ends of the first conductive channel, a second conductive channel layer including a second conductive channel, and a third and a fourth doped regions respectively located at two ends of the second conductive channel and a conductive buffer layer configured to reduce electrical interference between the first and the third doped regions; a first conductive layer in contact with the second doped region; a second conductive layer nested on the conductive channel structure and in contact with the first and the third doped regions; and a gate structure arranged around the first conductive channel and the second conductive channel.
Method of Making Nanosheet Fringe Capacitors or MEMS Sensors with Dissimilar Electrode Materials
A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.
METHODS AND SYSTEMS RELATING TO PHOTOCHEMICAL WATER SPLITTING
InGaN offers a route to high efficiency overall water splitting under one-step photo-excitation. Further, the chemical stability of metal-nitrides supports their use as an alternative photocatalyst. However, the efficiency of overall water splitting using InGaN and other visible light responsive photocatalysts has remained extremely low despite prior art work addressing optical absorption through band gap engineering. Within this prior art the detrimental effects of unbalanced charge carrier extraction/collection on the efficiency of the four electron-hole water splitting reaction have remained largely unaddressed. To address this growth processes are presented that allow for controlled adjustment and establishment of the appropriate Fermi level and/or band bending in order to allow the photochemical water splitting to proceed at high rate and high efficiency. Beneficially, establishing such material surface charge properties also reduces photo-corrosion and instability under harsh photocatalysis conditions.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a source/drain pattern disposed on a substrate and a source/drain contact connected to the source/drain pattern. The source/drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface.
VERTICALLY STACKED NANOWIRE FIELD EFFECT TRANSISTORS
A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.
Method for producing a sensor including a core-shell nanostructure
The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part.
Nanowire MOSFET with support structures for source and drain
Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.
Vertical nanowire transistor with axially engineered semiconductor and gate metallization
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
Recessed contact to semiconductor nanowires
A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.
SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION
Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.