Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure.

A method for forming a nanostructure array and a field effect transistor device on a substrate are provided. The method for forming the nanostructure array includes: providing a template solution comprising template nanostructures; depositing at least one template nanostructure onto the substrate by contacting the template solution with the substrate; and forming on the substrate at least one fixation structure each intersecting with all or a portion of the at least one template nanostructure to fix all or a portion of the at least one template nanostructure on the substrate.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of nanowires positioned above and parallel to a top surface of the substrate, wherein the plurality of nanowires comprises channel regions and source/drain regions positioned on each of both sides of the channel regions; a gate stack positioned surrounding the channel regions; and a magnetic storage structure positioned above a drain region of the plurality of nanowires and positioned adjacent to the gate stack. The magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity.

A retinal prosthesis system can comprise: a flexible substrate; a nanowire light detector which is placed on the substrate, and comprises one or more nanowires of which the resistance changes according to the applied light; one or more micro-electrodes which are placed on the substrate, are electrically connected to the nanowire light detector, and come in contact with retinal cells; and an electric power supply source for applying electric power to the nanowire light detector and the micro-electrodes. The retinal prosthesis system can be implemented into a very thin and flexible substrate type high resolution retinal system by manufacturing a nanowire light detector on a substrate in which micro-electrodes are implemented.

Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.

This invention describes the structure and function of an integrated multi-sensing system. Integrated systems described herein may be configured to form a microphone, pressure sensor, gas sensor, multi-axis gyroscope or accelerometer. The sensor uses a variety of different Field Effect Transistor technologies (horizontal, vertical, Si nanowire, CNT, SiC and III-V semiconductors) in conjunction with MEMS based structures such as cantilevers, membranes and proof masses integrated into silicon substrates. It also describes a configurable method for tuning the integrated system to specific resonance frequency using electronic design.

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal.

Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher V.sub.t (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.