A method for manufacturing a fin-type bipolar semiconductor device includes providing a substrate comprising a first region of a first conductivity type and a second region of a second conductivity type adjacent the first region, etching the substrate to form a third region in the first region, a first set of fins on the third region, a fourth region in the second region, and a second set of fins on the fourth region, performing a first implantation into a first portion of the second set of fins and a corresponding portion of the fourth region to form an emitter region of the first conductivity type, a remaining portion of the fourth region not being doped forming a base region adjacent the emitter region and forming a junction in the fourth region, and performing a second implantation into a second portion of the second set of fins different from the first portion.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

The present disclosure relates to a semiconductor structure and a manufacturing process therefor. Provided is a method for manufacturing a bipolar transistor with a trench structure, including providing a semiconductor substrate; fabricating a shallow trench isolation structure to define a device active area; forming an N-type well and a P-type well in the active area to define a first region, a second region and a third region of the bipolar transistor; etching a portion, adjacent to the shallow trench isolation structure, in the first region to form a trench; performing ion implantation to form an emitter, a base and a collector of the bipolar transistor; forming a salicide block structure in the trench; and forming a metal electrode of the bipolar transistor, wherein the emitter is formed in the first region. The present disclosure further provides a bipolar transistor with a trench structure.

SCRs are a must for ESD protection in low voltagehigh speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

A bipolar junction transistor (BJT) includes an emitter region, abase region on one side of the emitter region, and a collector region on the other side of the base region. The emitter region includes first fins extending along a first direction, a first metal gate extending across the first fins along a second direction, a second metal gate in parallel with the first metal gate, and an emitter contact plug on the first fins between the first metal gate and the second metal gate. The base region includes second fins extending along the first direction, the first metal gate and the second metal gate extending across the second fins along the second direction, and a base contact plug on the second fins between the first metal gate and the second metal gate. The emitter contact plug is aligned with the base contact plug.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.