At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.

A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant.

A heterojunction bipolar transistor may include a base epitaxially grown on a collector, an emitter epitaxially grown on the base, the emitter and the base being patterned into a fin, and a silicon oxide layer formed on sidewalls of the fin, the silicon oxide layer separating the base from a spacer. The heterojunction bipolar transistor may include the spacer formed on top of the silicon oxide layer and an interlayer dielectric formed on top of the spacer. The heterojunction bipolar transistor may also include a silicon germanium oxide layer formed on sidewalls of the base. The base may be made of silicon germanium. The emitter and the collector may be made of silicon. The base may be doped with a p-type dopant. The emitter and the collector may be doped with a n-type dopant.

An emitter mesa and a base electrode are arranged on a base mesa on a substrate. A base wiring line on the base electrode is connected to the base electrode via base openings. The emitter mesa includes a plurality of emitter fingers having a planar shape that is long in one direction. The emitter fingers include first and second emitter fingers. The base openings are arranged so as to be spaced apart in a longitudinal direction from first end portions of the first emitter fingers and are not arranged in a region obtained by extending the second emitter finger in the longitudinal direction. An end portion of the second emitter finger that is near the base openings protrudes in the longitudinal direction beyond the end portions of the first emitter fingers that are near the base openings.

A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

A semiconductor device includes a substrate, at least one heterojunction bipolar transistor including a semiconductor unit and an electrode unit, an insulation unit, and a heat dissipation unit. The insulation unit covers the substrate and the heterojunction bipolar transistor such that a collector electrode, a base electrode and an emitter electrode of the electrode unit are electrically isolated from one another. The insulation unit is formed with an opening to expose an electrode wire of the emitter electrode. The heat dissipation unit covers the electrode wire and is made of an electrically conductive and heat dissipating material, and has a thickness that is not less than 3 μm.

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.