A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alternative stress path that substantially bypasses the transistor.

In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The emitter mesa has a plurality of openings. The HBT further comprises a plurality of base metals in the plurality of openings connected to the base mesa.

A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.

A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.

A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.

A semiconductor device including: a semiconductor substrate having a drift region of the first conductivity type; a cathode region formed on the lower surface of the semiconductor substrate; a diode portion having the cathode region formed on the lower surface of the semiconductor substrate; the first dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and the first lead-out portion that is provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion is provided.

A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alterative stress path that substantially bypasses the transistor.

A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.