A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

Provided is a high ruggedness HBT, including a first emitter cap layer and a second emitter cap layer formed between an emitter layer and an ohmic contact layer, or only an emitter cap layer is formed between them. When the first and second emitter cap layers are provided, bandgaps of the first or second emitter cap layer are changed, and the ruggedness of the HBT is improved. When an emitter cap layer is provided, an electron affinity of at least a portion of the emitter cap layer is less than or approximately equal to an electron affinity of the emitter layer, and the ruggedness of the HBT is improved.

A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region and a collector region. The collector region may include a proton implant region having an edge aligned with an edge of the emitter region. In certain aspects, the HBT device also includes a base region disposed between the emitter region and the collector region.

A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.

On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component on a same die as the power amplifier, and a bias circuit on a different die than the power amplifier. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.