A semiconductor device comprises: an extrinsic base region (134); a first dielectric spacer (148, 348, 448) on at least a part of a sidewall of the extrinsic base region (134) adjacent to an emitter window region (142); an intrinsic base region (124, 224, 324, 424); a base link region (136, 236, 336, 436) coupling the intrinsic base region (124, 224, 324, 424) and the extrinsic base region (134); a collector region (108, 110) underlying the intrinsic base region (124, 224, 324, 424) and having a periphery underlying the base link region (136, 236, 336, 436); and a second dielectric spacer (154, 254, 354, 454), separating the base link region (136, 236, 336, 436) from at least the periphery of the collector region (108, 110); wherein said second dielectric spacer (154, 254, 354, 454) extends laterally beyond said first dielectric spacer (148, 348, 448) to underlie said emitter window region (142). A method for manufacturing a semiconductor device comprises: providing a semiconductor substrate (108); forming a lower dielectric layer (130, 230) on or above the substrate (108); forming an upper dielectric layer (132, 232, 432) on or above the lower dielectric layer (130, 230); forming an extrinsic base region (136, 236, 336, 436) on or above the upper dielectric layer (132, 232, 432); forming an opening (142) extending through the extrinsic base region (134); forming a first dielectric spacer (148, 348, 448) on at least a part of a sidewall of the extrinsic base region (134) adjacent to the opening (142); removing a part of the upper dielectric layer (132, 232, 432) in the opening (142); removing a part of the lower dielectric (130, 230) layer in the opening (142), such that a portion of the lower dielectric layer (130, 230) extends laterally beyond the first dielectric spacer (148, 348, 448) to underlie the opening (142), said lower dielectric layer (130, 230) providing a second dielectric spacer (154, 254, 354, 454); forming an intrinsic base region (124, 224, 324, 424) on or above the substrate (108) in the opening (142), the intrinsic base region (124, 224, 324, 424) being formed on or above a collector region (108, 110); and forming a base link region (136, 236, 336, 436) coupling the intrinsic base region (124, 224, 324, 424) to the extrinsic base region (134), wherein said second dielectric spacer (154, 254, 354, 454) separates th

In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.

A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

An epitaxial structure includes a composite base unit and an emitter unit. The composite base unit includes a first base layer and a second base layer formed on the first base layer. The first base layer is made of a material of In.sub.xGa.sub.(1-x)As.sub.(1-y)N.sub.y, in which 0<x?0.2, and 0?y?0.035, and when y is not 0, x=3y. The second base layer is made of a material In.sub.mGa.sub.(1-m)As, in which 0.03?m?0.2. The emitter unit is formed on the second base layer 12 opposite to the first base layer 11, and is made of an indium gallium phosphide-based material. A transistor including the epitaxial structure is also disclosed.

A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.

One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 310.sup.16 cm.sup.3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.

Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.