A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.

A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

An insulated gate bipolar transistor (IGBT) includes: a p base layer disposed close to a front surface of an n-type silicon substrate; and a deep n.sup.+ buffer layer and a shallow n.sup.+ buffer layer disposed close to a back surface of the n-type silicon substrate. The p base layer has a higher impurity concentration than the n-type silicon substrate. The deep n.sup.+ buffer layer and shallow n.sup.+ buffer layer have higher impurity concentrations than the n-type silicon substrate. The deep n.sup.+ buffer layer is disposed throughout a region close to the back surface in the n-type silicon substrate. The shallow n.sup.+ buffer layer is selectively disposed close to the back surface in the n-type silicon substrate. The shallow n.sup.+ buffer layer has a higher impurity concentration than the deep n.sup.+ buffer layer, and is shallower from the back surface than the deep n.sup.+ buffer layer.

A semiconductor device includes a semiconductor substrate having a drift region, and an edge terminal structure portion provided between the active region and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate. The edge terminal structure portion includes a plurality of guard rings of a second conductivity type which are in contact with the upper surface, and a high concentration region of the first conductivity type which has a higher doping concentration than the drift region and is provided, between adjacent two of the guard rings, from a position shallower than lower ends of the guard rings to a position deeper than the lower ends of the guard rings. Each of the guard rings has a region that is not covered by the high concentration region as viewed from a lower surface side.

An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

Provided is a semiconductor device, wherein: in a semiconductor substrate, a lifetime control region is provided from at least a part of a transistor portion to a diode portion; the transistor portion includes a main region, a boundary region located between the main region and the diode portion and overlapped with the lifetime control region, and a plurality of gate trench portions; the plurality of gate trench portions include a first gate trench portion provided in the main region and a second gate trench portion provided in the boundary region; and a gate resistance component of the first gate trench portion is different from a gate resistance component of the second gate trench portion.

A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.