A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region, and a gate structure is provided. The substrate has a first conductive type. The first doped region has the first conductive type and is formed in the substrate. The well has a second conductive type and is formed in the substrate. The second doped region has the second conductive type and is formed in the first doped region. The third doped region has the first conductive type and is formed in the well. The fourth doped region has the second conductive type and is formed in the well. The gate structure is disposed over the substrate and partially covers the first doped region and the well.

The re-combination center introduction region has re-combination centers introduced therein so that a density of the re-combination centers in the re-combination center introduction region is higher than a density of re-combination centers in a periphery of the re-combination center introduction region. The re-combination center introduction region continuously extends from the diode region to the peripheral region along a longitudinal direction of the diode region.

A p type anode layer is formed on a front surface of an n type drift layer in an active region. An n type buffer layer is formed on a rear surface of the n.sup.− type drift layer. An n type cathode layer and a p type cathode layer are formed side by side on a rear surface of the n type buffer layer. An n type layer is formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer. An extending distance of the n type layer to the active region side with an end portion of the active region as a starting point is represented by WGR1, and WGR1 satisfies 10 μm≦WGR1≦500 μm.

A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type between the first and second electrodes, first and second conductive regions between the first semiconductor region and the second electrode and electrically connected to the second electrode, a third electrode between the first and second conductive regions, second and third semiconductor regions of a second conductivity type respectively between the first and second conductive regions and the third electrode, and fourth and fifth semiconductor regions of the first conductivity type respectively between the second and third semiconductor regions and the second electrode. The third electrode extends in the first direction toward the first electrode farther than portions of the second and third semiconductor regions that are alongside the third electrode.

Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n.sup.− drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

An insulated gate bipolar transistor includes a semiconductor substrate, and the semiconductor substrate includes: a collector region doped in a first type, wherein the collector region includes a bump region; a first drift region doped in a second type and a second drift region doped in the second type; wherein the first drift region and the second drift region locate on a side of the collector region having the bump region, a profile contour of the first drift region matches a profile contour of the bump region, such that the second drift region does not contact the bump region, and a doping concentration of the first drift region is greater than a doping concentration of the second drift region; and a first active region and a second active region, formed at two opposite ends of the second drift region.

An IGBT region includes: an n-type carrier accumulation layer provided to be in contact with the n.sup.−-type drift layer on the first main surface side of the n.sup.−-type drift layer and having a higher n-type impurity concentration than the n.sup.−-type drift layer, a p-type base layer provided between the n-type carrier accumulation layer and the first main surface, an n.sup.+-type emitter layer selectively provided in a surface layer portion of the p-type base layer, and a gate electrode provided to face the n.sup.+-type emitter layer and the p-type base layer with an interposition of an insulating film. A diode region includes a p-type anode layer provided between the n.sup.−-type drift layer and the first main surface and provided to a position deeper from the first main surface than a boundary between the n-type carrier accumulation layer and the n.sup.−-type drift layer.

Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.