An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

A device includes a substrate, a drift region in the substrate, a base region above the drift region; a first high concentration region selectively formed in a part on a surface side of the base region and having a concentration higher than the drift region; a trench portion formed in a front surface of the substrate and including extending portions; and mesa portions between the extending portions. The mesa portions includes first mesa portions having the first high concentration region and second mesa portions not having the first high concentration region, the trench portion includes a first trench portion having an first conductive portion (a gate conductive potion) and adjacent to the first mesa portion, a second trench portion having the first conductive portion and adjacent to the second mesa portion, and a third trench portion having an second conductive portion and adjacent to the first or second mesa portion.

According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region.

A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.

Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.

In an RFC diode, a semiconductor substrate includes an n− drift layer, an n buffer layer, and a diffusion layer provided between and in contact with the n buffer layer and a second metal layer. The diffusion layer includes an n+ cathode layer provided in contact with the n buffer layer and the second metal layer in a diode region. The n+ cathode layer includes a first n+ cathode layer in contact with the second metal layer and a second n+ cathode layer provided between the first n+ cathode layer and the n buffer layer in contact with the n buffer layer. Crystal defect density of the first n+ cathode layer is higher than crystal defect density of another diffusion layer.

To provide a semiconductor device having excellent conduction characteristics of a transistor portion and a diode portion. The semiconductor device having a transistor portion and a diode portion, the semiconductor device includes: a drift region of a first conductivity type provided on a semiconductor substrate, a first well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, an anode region of the second conductivity provided on the upper surface side of the semiconductor substrate, in the diode portion, and a first high concentration region of a second conductivity type which is provided in contact with a first well region between the anode region and the first well region, and has a higher doping concentration than the anode region.

A semiconductor device includes first and second electrodes, a semiconductor part between the first and second electrodes, first to third control electrodes between the semiconductor part and the first electrode, first and second control terminals electrically connected respectively to the first and second control electrodes. The first to third control electrodes each are provided in a trench of the semiconductor part. The third control electrode is provided between the first and second control electrodes. The semiconductor part includes first and third layers of a first conductivity type, and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The first electrode is electrically connected to the second and third layers.

A semiconductor device, allowing easy hole extraction, including a semiconductor substrate having drift and base regions; and transistor and diode portions, in which trench portions and mesa portions are formed, is provided. The transistor portion includes emitter and contact regions above the base region and exposed to an upper surface of the semiconductor substrate. The emitter region has a higher concentration than the drift region. The contact region has a higher concentration than the base region. The mesa portions include boundary mesa portion(s) at a boundary between the transistor and diode portions. The trench portions include dummy trench portion(s) provided adjacent to a trench portion adjacent to the boundary mesa portion(s) and provided on the transistor portion side relative to the trench portion adjacent to the boundary mesa portion(s). The boundary mesa portion(s) include a base boundary mesa portion in which the base region is exposed to the upper surface.