A power electronic arrangement includes a semiconductor switch structure configured to assume a forward conducting state. A steady-state current carrying capability of the semiconductor switch structure in the forward conducting state is characterized by a nominal current. The semiconductor switch structure is configured to conduct, in the forward conducting state, at least a part of a forward current in a forward current mode of the power electronic arrangement. A diode structure electrically connected in antiparallel to the semiconductor switch structure is configured to conduct at least a part of a reverse current in a reverse mode of the power electronic arrangement. A thyristor structure electrically connected in antiparallel to the semiconductor switch structure has a forward breakover voltage than a diode on-state voltage of the diode structure at a critical diode current value, the critical diode current value amounting to at most five times the nominal current.

A semiconductor device includes a semiconductor body having opposite first and second surfaces, a gate region, and an active region arranged adjacent to the gate region in a horizontal direction. A first emitter, a first base, and a second base are arranged consecutively between the second and first surfaces in a vertical direction. A front-facing emitter is arranged in the active region and extends in the vertical direction from the first surface to the second base. Short-circuit regions extend from the first surface through the front-facing emitter to the second base. The active region has, in the horizontal direction, a first edge region adjacent to the gate region, a failure region adjacent to the first edge region, and a second edge region adjacent to the failure region. An average density of the short-circuit regions in the failure region is lower than in both edge regions.

This invention discloses an insulating gate bipolar transistor (IGBT) device that comprises a substrate including a semiconductor layer of a first conductivity type on the top of the bottom semiconductor layer of a second conductivity type and supporting buried layer of a second conductivity type disposed below a top layer of the first conductivity type. The IGBT further has a plurality of MOS transistor cells each having a planar gate disposed on a top surface of the top layer wherein each of the planar gates extended between two adjacent body regions of the second conductivity type encompassing a emitter region of the first conductivity type wherein the body regions and emitter regions are near a top portion of the top layer of the first conductivity type. The IGBT further includes a trench gate vertically extending from the top portion of the top layer adjacent to a body region downwardly to the buried layer of the second conductivity. Furthermore, the device includes lightly doped region in the top layer of the first conductivity type that is disposed next to the trench gate below the body region of the second conductivity type above the buried layer of the second conductivity type.

The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 m from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

A semiconductor device that can detect temperature appropriately is provided. A semiconductor device provided with a semiconductor substrate in which one or more transistor portions and one or more diode portions are provided is provided, including: a temperature detecting portion provided above the top surface of the semiconductor substrate and having a longitudinal side in a predetermined longitudinal direction; a top surface electrode provided above the top surface of the semiconductor substrate; and one or more external lines that have a connecting part connected with the top surface electrode and electrically connect the top surface electrode to a circuit outside the semiconductor device. The temperature detecting portion extends across the one or more transistor portions and the one or more diode portions in the longitudinal direction, and the connecting part of at least one of the external lines is arranged around the temperature detecting portion when seen from above.

The present disclosure relates to four-layer latching devices having improved reverse current capabilities. The devices have a localized doping spike region in the upper base region, the lower base region, or both. The localized doping spike regions have a localized doping concentration that is greater than the doping concentration of the layer where the localized doping spike region is located. Within the base regions the localized spikes are located next to the corresponding upper emitter region, lower emitter region, or both.

An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.

An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.

A thyristor is disclosed with a plurality of emitter shorts at points in the cathode region. The points define a Delaunay triangulation with a plurality of triangles. For a first subset of triangles a coefficient of variation of the values q.sub.T,l with lS.sub.1 is smaller than 0.1, and/or an absolute value of a skewedness of the geometric quantities q.sub.T,l with lS.sub.1 is smaller than 5, and/or a Kurtosis of the geometric quantities q.sub.T,l with lS.sub.1 is smaller than 20. For a second subset of triangles, a quotient of a standard deviation of the quantities q.sub.T,m with mS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lS.sub.1 is less than 1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.010.sup.2.