A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of .sup.18O greater than 10 percent.

A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

A semiconductor device may include a semiconductor substrate, and a superlattice on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.

A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device having a co-integrated RTD and HEMT. A semiconductor device can comprise an RTD and an HEMT that are co-integrated along a substrate. A fabrication method can comprise providing a heterostructure comprising a plurality of transistor layers of an HEMT, forming on the vertical stack a template structure comprising an opening, a cavity and a seed structure, the seed structure comprising a seed material and a seed surface, and growing a plurality of diode layers of an RTD within the cavity of the template structure from the seed surface, wherein the RTD and HEMT are co-integrated along a substrate.