A semiconductor substrate includes a base substrate, a first epitaxial layer having a first conductivity type on the base substrate, a second epitaxial layer having the first conductivity type on the first epitaxial layer, a first well region having a second conductivity type different from the first conductivity type, in the first epitaxial layer and the second epitaxial layer, and a second well region which is spaced apart from the first well region and has the second conductivity type, in the first epitaxial layer and the second epitaxial layer, wherein a doping concentration of the first epitaxial layer is greater than a doping concentration of the second epitaxial layer, and a depth of each of the first well region and the second well region is greater than a thickness of the second epitaxial layer.

A semiconductor device includes a substrate that includes an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode on the channel pattern, an active contact electrically connected to the source/drain pattern, and a gate contact electrically connected to the gate electrode. The active contact includes a first barrier pattern, a first seed pattern on the first barrier pattern, a first fill pattern on the first seed pattern, and a first metal-containing pattern between the first seed pattern and the first fill pattern. The first metal-containing pattern includes tungsten nitride. A nitrogen concentration of the first metal-containing pattern decreases in a direction toward the substrate.

An exemplary semiconductor apparatus includes a substrate that includes a first semiconductor. The substrate includes a main body and first and second island portions protruding upward from the main body. The apparatus also includes a bottom dielectric isolation layer that covers the substrate; a PFET with a plurality of gate-all-around (GAA) vertical channel fins above the first island portion and the bottom dielectric isolation layer; and an NFET with a plurality of gate-all-around (GAA) horizontal nanosheet layers above the second island portion and the bottom dielectric isolation layer.

An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

A device includes an isolation structure, a source/drain epi-layer, a contact, a first dielectric layer, and a second dielectric layer. The isolation structure is embedded in a substrate. The source/drain epi-layer is embedded in the substrate and is in contact with the isolation structure. The contact is over the source/drain epi-layer. The first dielectric layer wraps the contact. The second dielectric layer is between the contact and the first dielectric layer. The first and second dielectric layers include different materials, and a portion of the source/drain epi-layer is directly between a bottom portion of the second dielectric layer and a top portion of the isolation structure.

A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.