The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

A switched mode power converter is provided herein and comprises a cycloconverter comprising a plurality of switches, wherein each switch of the plurality of switches is a native four quadrant bi-directional switch with a common drift region configured to allow current flow in a first direction from a first source terminal to second source terminal and in a second direction from the second source terminal to the first direction.

A semiconductor device (100, 100′, 100″) and a method for manufacturing a semiconductor device (100, 100′, 100″). The semiconductor device (100, 100′, 100″) includes a substrate (104, 106), a GaN layer (112), and an AlGaN layer (114). The GaN layer (112) is located between the substrate (104, 106) and the AlGaN layer (114). The device further includes at least one contact (130, 132, 134), comprising a central portion (150) and an edge portion (152), and a passivation layer (160) located at least between the edge portion (152) of the contact (130, 132, 134) and the AlGaN layer (114). The edge portion (152) is spaced apart from an upper surface of the passivation layer (160). The edge portion (152) may be spaced apart from the passivation layer (160) by a further layer (170) or by an air gap (172).

A semiconductor device (100, 100′, 100″) and a method for manufacturing a semiconductor device (100, 100′, 100″). The semiconductor device (100, 100′, 100″) includes a substrate (104, 106), a GaN layer (112), and an AlGaN layer (114). The GaN layer (112) is located between the substrate (104, 106) and the AlGaN layer (114). The device further includes at least one contact (130, 132, 134), comprising a central portion (150) and an edge portion (152), and a passivation layer (160) located at least between the edge portion (152) of the contact (130, 132, 134) and the AlGaN layer (114). The edge portion (152) is spaced apart from an upper surface of the passivation layer (160). The edge portion (152) may be spaced apart from the passivation layer (160) by a further layer (170) or by an air gap (172).

A semiconductor device includes a carrier generation layer disposed on a channel layer, a source contact and a drain contact disposed on the carrier generation layer, and a gate contact disposed between the source contact and the drain contact. The semiconductor device further includes a number N of conductive stripes disposed directly on the carrier generation layer in an area between the drain contact and the gate contact, and a number M of conductive transverse stripes disposed directly on the carrier generation layer in the area between the drain contact and the gate contact. Each of the N conductive stripes extends from and is electrically coupled to the drain contact. Each of the M conductive transverse stripes is aligned non-parallel to the N conductive stripes and is not in direct physical contact with the N conductive stripes.

A semiconductor device includes a carrier generation layer disposed on a channel layer, a source contact and a drain contact disposed on the carrier generation layer, and a gate contact disposed between the source contact and the drain contact. The semiconductor device further includes a number N of conductive stripes disposed directly on the carrier generation layer in an area between the drain contact and the gate contact, and a number M of conductive transverse stripes disposed directly on the carrier generation layer in the area between the drain contact and the gate contact. Each of the N conductive stripes extends from and is electrically coupled to the drain contact. Each of the M conductive transverse stripes is aligned non-parallel to the N conductive stripes and is not in direct physical contact with the N conductive stripes.

A source electrode (5), a drain electrode (6) and a T-shaped gate electrode (9) are formed on a GaN-based semiconductor layer (3,4) to form a transistor. An insulating film (10,11) covering the T-shaped gate electrode (9) is formed. A property of the transistor is evaluated to obtain an evaluation result. A film type, a film thickness or a dielectric constant of the insulating film (10,11) is adjusted in accordance with the evaluation result to make a property of the transistor close to a target property.

A source electrode (5), a drain electrode (6) and a T-shaped gate electrode (9) are formed on a GaN-based semiconductor layer (3,4) to form a transistor. An insulating film (10,11) covering the T-shaped gate electrode (9) is formed. A property of the transistor is evaluated to obtain an evaluation result. A film type, a film thickness or a dielectric constant of the insulating film (10,11) is adjusted in accordance with the evaluation result to make a property of the transistor close to a target property.

Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.

Disclosed herein are integrated circuit (IC) structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. One example IC structure includes an III-N transistor in a first layer over a support structure (e.g., a substrate) and a TFT in a second layer over the support structure, where the first layer is between the support structure and the second layer. Another example IC structure includes a III-N semiconductor material and a TFT, where at least a portion of a channel material of the TFT is over at least a portion of the III-N semiconductor material.