The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a nitride semiconductor layer disposed on the substrate, a first gate stack in contact with the nitride semiconductor layer, and a resistor laterally spaced apart from the first gate stack and electrically connected to first gate stack. The resistor comprises a first conductive terminal in contact with the nitride semiconductor layer, a second conductive terminal in contact with the nitride semiconductor layer; a first doped region of the nitride semiconductor layer between the first conductive terminal and the second conductive terminal; and a first conductive region of the nitride semiconductor layer in contact with the first conductive terminal and the second conductive terminal.

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

A nitride-based semiconductor device includes first and second nitride-based semiconductor layers, first electrodes, doped nitride-based semiconductor layers, a second electrode, and gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion surrounding the active portion. The first electrodes are disposed over the second nitride-based semiconductor layer. The first electrodes, doped nitride-based semiconductor layers, the gate electrode, and the second electrode are disposed over the second nitride-based semiconductor layer. Each of the doped nitride-based semiconductor layers has a side surface facing away from the second electrode and spaced apart from the interface.

A nitride-based semiconductor device includes first and second nitride-based semiconductor layers, first electrodes, doped nitride-based semiconductor layers, a second electrode, and gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion surrounding the active portion. The first electrodes are disposed over the second nitride-based semiconductor layer. The first electrodes, doped nitride-based semiconductor layers, the gate electrode, and the second electrode are disposed over the second nitride-based semiconductor layer. Each of the doped nitride-based semiconductor layers has a side surface facing away from the second electrode and spaced apart from the interface.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a pair of first electrodes, a second electrode, a doped nitride-based semiconductor layer, and a pair of gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion that is non-semi-conducting and surrounds the active portion to form an interface therebetween. The first electrodes are disposed over the second nitride-based semiconductor layer. The second electrode are disposed over the second nitride-based semiconductor layer and between the first electrodes. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the first electrodes and surrounding the second electrode. The gate electrodes are disposed over the doped nitride-based semiconductor layer and located at opposite sides of the second electrode.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a pair of first electrodes, a second electrode, a doped nitride-based semiconductor layer, and a pair of gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion that is non-semi-conducting and surrounds the active portion to form an interface therebetween. The first electrodes are disposed over the second nitride-based semiconductor layer. The second electrode are disposed over the second nitride-based semiconductor layer and between the first electrodes. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the first electrodes and surrounding the second electrode. The gate electrodes are disposed over the doped nitride-based semiconductor layer and located at opposite sides of the second electrode.

A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, a doped III-V semiconductor layer, a gate electrode, a first and second source/drain (S/D) electrodes. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and has first and second current-leakage barrier portions which extends downward from atop surface of the doped III-V semiconductor layer. The gate electrode is disposed above the doped III-V semiconductor layer, in which the gate electrode has a pair of opposite edges between the first and second current-leakage barrier portions. One of the edges of the gate electrode coincides with the first current-leakage barrier portion. The first current-leakage barrier portion is located between the first S/D electrode and the gate electrode. The second current-leakage barrier portion is located between the second S/D electrode and the gate electrode.