A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.

A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.

In one example, a sensor includes a heterojunction bipolar transistor and component sensing surface coupled to the heterojunction bipolar transistor via an extended base component. In another example, a biosensor for detecting a target analyte includes a heterojunction bipolar transistor and a sensing surface. The heterojunction bipolar transistor includes a semiconductor emitter including an emitter electrode for connecting to an emitter voltage, a semiconductor collector including a collector electrode for connecting to a collector voltage, and a semiconductor base positioned between the semiconductor emitter and the semiconductor collector. The sensing surface is coupled to the semiconductor base of the heterojunction bipolar transistor via an extended base component and includes a conducting film and a reference electrode.

In one example, a sensor includes a heterojunction bipolar transistor and component sensing surface coupled to the heterojunction bipolar transistor via an extended base component. In another example, a biosensor for detecting a target analyte includes a heterojunction bipolar transistor and a sensing surface. The heterojunction bipolar transistor includes a semiconductor emitter including an emitter electrode for connecting to an emitter voltage, a semiconductor collector including a collector electrode for connecting to a collector voltage, and a semiconductor base positioned between the semiconductor emitter and the semiconductor collector. The sensing surface is coupled to the semiconductor base of the heterojunction bipolar transistor via an extended base component and includes a conducting film and a reference electrode.

A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.

A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.

This disclosure relates to methods for forming bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. In some embodiments, the methods include forming a sub-collector. In some embodiments the methods include forming a primary collector region with at least one grading having a doping concentration that decreases away from the sub-collector. In some embodiments the methods further include forming a secondary collector region to abut a base of the bipolar transistor and having a doping concentration of at least about 3×10.sup.16 cm.sup.−3 at an interface with the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

This disclosure relates to methods for forming bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. In some embodiments, the methods include forming a sub-collector. In some embodiments the methods include forming a primary collector region with at least one grading having a doping concentration that decreases away from the sub-collector. In some embodiments the methods further include forming a secondary collector region to abut a base of the bipolar transistor and having a doping concentration of at least about 3×10.sup.16 cm.sup.−3 at an interface with the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

The invention relates to a method for producing a semiconductor structure, characterised in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, −⅓) and (0, −⅔) between the central line (0, 0) and the integer order line (0, −1), and two fractional order diffraction lines (0, ⅓) and (0, ⅔) between the central line (0, 0) and the integer order line (0, 1).

The invention relates to a method for producing a semiconductor structure, characterised in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, −⅓) and (0, −⅔) between the central line (0, 0) and the integer order line (0, −1), and two fractional order diffraction lines (0, ⅓) and (0, ⅔) between the central line (0, 0) and the integer order line (0, 1).