There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device includes comprising a gate structure including a gate electrode and a gate capping pattern on an upper surface of the gate electrode; a source/drain pattern on at least one side of the gate structure; and a source/drain contact on and connected with an upper surface of the source/drain pattern, the source/drain contact extending along a sidewall of the gate electrode, wherein an upper surface of the source/drain contact includes a convex curved surface.

A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

A semiconductor device includes a substrate, an active pattern disposed on the substrate and that extends in a first horizontal direction, a field insulating layer disposed on the substrate and that surrounds a sidewall of the active pattern, a gate electrode disposed on the field insulating layer and that extends in a second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first interlayer insulating layer disposed on the field insulating layer and that surrounds a portion of a sidewall of the source/drain region, a second interlayer insulating layer disposed on the first interlayer insulating layer and that surrounds a sidewall of the gate electrode, and a source/drain contact that penetrates through the second interlayer insulating layer and is electrically connected to the source/drain region. The source/drain contact includes a skirt that protrudes from a lower sidewall toward the second interlayer insulating.

A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 10.sup.18 cm.sup.−3. A semiconductor structure and a manufacturing method are also provided.

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.

A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer expose the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and is connected to the source/drain contact.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer, wherein a first portion of the contact structure is between the first source/drain layer and the substrate.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a first terminal and a second terminal electrically connected to the semiconductor film. The second terminal is electrically connected to the light-emitting element. A region in which the first terminal overlaps with the gate electrode can be smaller than a region in which the second terminal overlaps with the gate electrode.