In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.

In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.

A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole.

A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape

Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low R.sub.DS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication plants that cannot or typically do not make superjunction MOSFETs.

A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.

A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an upper surface of the substrate. A fin structure is disposed on the substrate and extended vertically from the upper surface of the substrate. The fin structure includes a first end portion and a second end portion arranged along the first direction. A bottom surface of a first end portion of the fin structure and a bottom surface of a second end portion of the fin structure overlap the lower drain and the lower source, respectively. The fin structure includes a sidewall having a lower sidewall region, a center sidewall region and an upper sidewall region. A gate electrode surrounds the center side sidewall region of the fin structure.

A semiconductor device includes: a semiconductor layer; a first electrode that is in ohmic contact with part of the semiconductor layer; an insulating film that is formed over from the semiconductor layer to the first electrode and has an opening area on an inner side of a first edge of the first electrode; a second electrode that is located at a position different from the first electrode and is formed on at least one of the insulating film and the semiconductor layer; and a third electrode that is made of an identical component with a component of the second electrode and is formed on the first electrode through the opening area and is also formed over from the first electrode to an inner side of the first edge on the insulating film.